AD9834 Analog Devices, AD9834 Datasheet - Page 17

• Manufacturer Part Number: AD9834
• Description: +2.5V to +5.5V, 50MHz, Low Power (25mW) Complete DDS With on Board Comparator in 20-pin Tssop Package
• Manufacturer: Analog Devices

GROUNDING AND LAYOUT
The printed circuit board that houses the AD9834 should
be designed so that the analog and digital sections are
separated and confined to certain areas of the board. This
facilitates the use of ground planes which can be separated
easily.
ground planes as it gives the best shielding. Digital and
analog ground planes should only be joined in one place.
If the AD9834 is the only device requiring an AGND to
DGND connection, then the ground planes should be
connected at the AGND and DGND pins of the AD9834.
If the AD9834 is in a system where multiple devices re-
quire AGND to DGND connections, the connection
should be made at one point only, a star ground point that
should be established as close as possible to the AD9834.
Avoid running digital lines under the device as these will
couple noise onto the die. The analog ground plane should
be allowed to run under the AD9834 to avoid noise cou-
pling. The power supply lines to the AD9834 should use
as large a track as is possible to provide low impedance
paths and reduce the effects of glitches on the power sup-
ply line. Fast switching signals such as clocks should be
shielded with digital ground to avoid radiating noise to
other sections of the board. Avoid crossover of digital and
analog signals. Traces on opposite sides of the board
should run at right angles to each other. This will reduce
the effects of feedthrough through the board.
technique is by far the best but is not always possible with
a double-sided board. In this technique, the component
side of the board is dedicated to ground planes while sig-
nals are placed on the other side.
Good decoupling is important.
supplies to the AD9834 are independent and separately
pinned out to minimize coupling between analog and digi-
tal sections of the device. All analog and digital supplies
should be decoupled to AGND and DGND respectively
with 0.1 µF ceramic capacitors in parallel with 10 µF
tantalum capacitors. To achieve the best from the
decoupling capacitors, they should be placed as close as
possible to the device, ideally right up against the device.
In systems where a common supply is used to drive both
the AVDD and DVDD of the AD9834, it is recommended
that the system’s AVDD supply be used. This supply
should have the recommended analog supply decoupling
between the AVDD pins of the AD9834 and AGND and
the recommended digital supply decoupling capacitors
between the DVDD pins and DGND.
REV PrL
A minimum etch technique is generally best for
PRELIMINARY TECHNICAL DATA
The analog and digital
A microstrip
–17–
INTERFACING TO MICROPROCESSORS
The AD9834 has a standard serial interface which allows
the part to interface directly with several microprocessors.
The device uses an external serial clock to write the data/
control information into the device. The serial clock can
have a frequency of 40 MHz maximum. The serial clock
can be continuous or, it can idle high or low between
write operations.
written to the AD9834, FSYNC is taken low and is held
low while the 16 bits of data are being written into the
AD9834. The FSYNC signal frames the 16 bits of infor-
mation being loaded into the AD9834.
AD9834 to ADSP-21xx Interface
Figure 12 shows the serial interface between the AD9834
and the ADSP-21xx. The ADSP-21xx should be set up to
operate in the SPORT Transmit Alternate Framing Mode
(TFSW = 1).
the SPORT control register and should be configured as
follows:
Transmission is initiated by writing a word to the Tx reg-
ister after the SPORT has been enabled. The data is
clocked out on each rising edge of the serial clock and
clocked into the AD9834 on the SCLK falling edge.
AD9834 to 68HC11/68L11 Interface
Figure 13 shows the serial interface between the AD9834
and the 68HC11/68L11 microcontroller. The
microcontroller is configured as the master by setting bit
MSTR in the SPCR to 1 and, this provides a serial clock
on SCK while the MOSI output drives the serial data line
SDATA. Since the microcontroller does not have a dedi-
cated frame sync pin, the FSYNC signal is derived from a
port line (PC7). The set up conditions for correct opera-
tion of the interface are as follows:
When data is being transmitted to the AD9834, the
FSYNC line is taken low (PC7). Serial data from the
68HC11/68L11 is transmitted in 8-bit bytes with only 8
falling clock edges occuring in the transmit cycle. Data is
transmitted MSB first. In order to load data into the
AD9834, PC7 is held low after the first 8 bits are trans-
ferred and a second serial write operation is performed to
the AD9834. Only after the second 8 bits have been trans-
Internal clock operation (ISCLK = 1)
Active low framing (INVTFS = 1)
16-bit word length (SLEN = 15)
Internal frame sync signal (ITFS = 1)
Generate a frame sync for each write (TFSR = 1).
SCK idles high between write operations (CPOL = 0)
data is valid on the SCK falling edge (CPHA = 1).
Figure 11. ADSP2101/ADSP2103 to AD9834 Interface
The ADSP-21xx is programmed through
When data/control information is being
AD9834