AD9923 Analog Devices, AD9923 Datasheet - Page 40

• Manufacturer Part Number: AD9923
• Manufacturer: Analog Devices

AD9880
0x13
0x14
STATUS OF DETECTED SIGNALS
0x15
Table 15. Hsync0 Detection Results
Detect
0
1
0x15
Table 16. Hsync1 Detection Result
Detect
0
1
0x15
7-0
This register allows the internally generated Coast
signal to be applied prior to the Vsync signal. This is
necessary in cases where pre-equalization pulses are
present. The step size for this control is one Hsync
period. For Precoast to work correctly, it is necessary
for the Vsync filter (0x21, Bit 5) and sync processing
filter (0x21 Bit 7) both to be either enabled or
disabled. The power-up default is 0.
7-0
This register allows the internally generated Coast
signal to be applied following the Vsync signal. This is
necessary in cases where post-equalization pulses are
present. The step size for this control is one Hsync
period. For Postcoast to work correctly, it is necessary
for the Vsync filter (0x21, Bit 5) and sync processing
filter (0x21, Bit 7) both to be either enabled or
disabled. The power-up default is 0.
7
Indicates if Hsync0 is active. This bit is used to
indicate when activity is detected on the Hsync0 input
pin. If Hsync is held high or low, activity is not
detected. The sync processing block diagram shows
where this function is implemented. 0 = Hsync0 not
active. 1 = Hsync0 is active.
6
Indicates if Hsync1 is active. This bit is used to indi-
cate when activity is detected on the Hsync1 input pin.
If Hsync is held high or low, activity is not detected.
The sync processing block diagram shows where this
function is implemented. 0 = Hsync1 not active.
1 = Hsync1 is active.
5
Indicates if Vsync0 is active. This bit is used to
indicate when activity is detected on the Vsync0 input
pin. If Vsync is held high or low, activity is not
detected. The sync processing block diagram shows
where this function is implemented. 0 = Vsync0 not
active. 1 = Vsync0 is active.
Precoast
Postcoast
Hsync0 Detection Bit
Hsync1 Detection Bit
Vsync0 Detection Bit
Result
No activity detected
Activity detected
Result
No activity detected
Activity detected
Rev. 0 | Page 40 of 64
Table 17. Vsync0 Detection Results
Detect
0
1
0x15
Table 18. Vsync1 Detection Results
Detect
0
1
0x15
Table 19. SOG0 Detection Result
Detect
0
1
0x15
Table 20. SOG1 Detection Results
Detect
0
1
4
Indicates if Vsync1 is active. This bit is used to
indicate when activity is detected on the Vsync1 input
pin. If Vsync is held high or low, activity is not
detected. The sync processing block diagram shows
where this function is implemented. 0 = Vsync1 not
active. 1 = Vsync1 is active.
3
Indicates if SOG0 is active. This bit is used to indicate
when activity is detected on the SOG0 input pin. If
SOG is held high or low, activity is not detected. The
sync processing block diagram shows where this
function is implemented. 0 = SOG0 not active.
1 = SOG0 is active.
2
Indicates if SOG1 is active. This bit is used to indicate
when activity is detected on the SOG1 input pin. If
SOG is held high or low, activity is not detected. The
sync processing block diagram shows where this
function is implemented. 0 = SOG1 not active.
1 = SOG1 is active.
Vsync1 Detection Bit
SOG0 Detection Bit
SOG1 Detection Bit
Result
No activity detected
Activity detected
Result
No activity detected
Activity detected
Result
No activity detected
Activity detected
Result
No activity detected
Activity detected