ADZS-BF537-EZLITE Analog Devices, ADZS-BF537-EZLITE Datasheet - Page 37

• Manufacturer Part Number: ADZS-BF537-EZLITE
• Description: Specifications: Type: DSP ; Contents: Evaluation Board, Software and Documentation ; For Use With/Related Products: ADSP-BF537 ; Lead Free Status: Lead Free ; RoHS Status: RoHS Compliant
• Manufacturer: Analog Devices

Parallel Peripheral Interface Timing
Table 29
Figure 23 on Page 42
operations.
Table 29. Parallel Peripheral Interface Timing
1
Parameter
Timing Requirements
t
t
Timing Requirements—GP Input and Frame Capture Modes
t
t
t
t
Switching Characteristics—GP Output and Frame Capture Modes
t
t
t
t
PPI_CLK frequency cannot exceed f
PCLKW
PCLK
SFSPE
HFSPE
SDRPE
HDRPE
DFSPE
HOFSPE
DDTPE
HDTPE
and
Figure 16 on Page
PPI_CLK Width
PPI_CLK Period
External Frame Sync Setup Before PPI_CLK
External Frame Sync Hold After PPI_CLK
Receive Data Setup Before PPI_CLK
Receive Data Hold After PPI_CLK
Internal Frame Sync Delay After PPI_CLK
Internal Frame Sync Hold After PPI_CLK
Transmit Data Delay After PPI_CLK
Transmit Data Hold After PPI_CLK
PPI_FS1/2
PPI_DATA
PPI_FS1/2
PPI_DATA
PPI_CLK
PPI_CLK
describe parallel peripheral interface
t
HOFSPE
SCLK
FRAME SYNC
DRIVEN
37,
/2.
t
SFSPE
1
1
Figure 20 on Page
FRAME SYNC SAMPLED
t
t
SDRPE
DFSPE
DATA SAMPLED /
Figure 17. PPI GP Rx Mode with External Frame Sync Timing
Figure 16. PPI GP Rx Mode with Internal Frame Sync Timing
SAMPLED
DATA
Rev. I | Page 37 of 68 | July 2010
40, and
t
PCLKW
t
HFSPE
t
HDRPE
t
SDRPE
FRAME SYNC SAMPLED
t
PCLK
DATA SAMPLED /
ADSP-BF534/ADSP-BF536/ADSP-BF537
t
PCLKW
t
HDRPE
t
PCLK
Min
6.0
15.0
6.7
1.0
3.5
1.5
1.7
1.8
Max
8.0
8.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns