MAX109 Maxim Integrated Products, MAX109 Datasheet - Page 19

• Manufacturer Part Number: MAX109
• Description: 2.2Gsps ADC
• Manufacturer: Maxim Integrated Products

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Figure 6. Timing Diagram for SDR Mode, f CLK / 4 Mode
(double data rate), and QDR (quadruple data rate).
Setting these two bits for different modes allows the
user to update and process the outputs at one-quarter
(SDR mode), one-eighth (DDR mode), or one-sixteenth
(QDR mode) the sampling clock (Table 2), relaxing the
need for an ultra-fast FPGA or data-capture interface.
Data is presented on all four ports of the converter-
demultiplexer circuit outputs. Note that there is a data
latency between the sampled data and each of the out-
put ports. The data latency is 10.5 clock cycles for
PortA, 9.5 clock cycles for PortB, 8.5 clock cycles for
PortC, and 7.5 clock cycles for PortD. This holds true for
all demultiplexer modes. Figures 6, 7, and 8 display the
demultiplexer timing for f
modes.
The MAX109 features a PRN generator that enables the
user to test the demultiplexed digital outputs at full
clock speed and with a known test pattern. The PRN
generator is a combination of shift register and feed-
back logic with 255 states. When PRN is high, the inter-
PORTC DATA
PORTD DATA
PORTA DATA
PORTB DATA
Pseudorandom Number (PRN) Generator
DCON
CLKN
DCOP
CLKP
NOTE: THE LATENCY TO THE D PORT IS 7.5 CLOCK CYCLES, THE LATENCY TO THE C PORT IS 8.5 CLOCK CYCLES, THE LATENCY TO THE B
PORT IS 9.5 CLOCK CYCLES, AND THE LATENCY TO THE A PORT IS 10.5 CLOCK CYCLES. ALL DATA PORTS (PORTA, PORTB, PORTC, AND
PORTD) ARE UPDATED ON THE RISING EDGE OF THE DCOP CLOCK.
N
8-Bit, 2.2Gsps ADC with Track/Hold Amplifier
ADC SAMPLE NUMBER
N + 1 N + 2 N + 3
______________________________________________________________________________________
CLK
/ 4, f
N + 4
and 1:4 Demultiplexed LVDS Outputs
CLK
t
PD1
N + 5
/ 8, and f
ADC SAMPLES ON THE RISING EDGE OF CLKP
N + 6 N + 7
t
PWH
CLK
/ 16
N + 8 N + 9 N + 10 N + 11 N + 12 N + 13 N + 14 N + 15 N + 16 N + 17 N + 18 N + 19
Table 3. Pseudorandom Number
Generator Patterns
t
PWL
N
SAMPLE HERE
CODE
250
251
252
253
254
255
10
—
—
1
2
3
4
5
6
7
8
9
t
CLK
N + 1
N + 2
N + 3
N + 4
OUTPUT PRN PATTERN
0 0 0 0 0 0 0 1
0 0 0 0 0 0 1 0
0 0 0 0 0 1 0 0
0 0 0 0 1 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 1 0 0 0 1 1 1
1 0 0 0 1 1 1 0
0 0 0 1 1 1 0 0
0 0 1 1 1 0 0 0
0 0 1 1 0 1 0 0
0 1 1 0 1 0 0 0
1 1 0 1 0 0 0 0
1 0 1 0 0 0 0 0
0 1 0 0 0 0 0 0
1 0 0 0 0 0 0 0
t
PD2
—
—
N + 5
N + 6
N + 7
N + 8
19