MAX1304 Maxim, MAX1304 Datasheet - Page 6

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MAX1304

Manufacturer Part Number
MAX1304
Description
8-/4-/2-Channel / 12-Bit / Simultaneous-Sampling ADCs with 10V / 5V / and 0 to +5V Analog Input Ranges
Manufacturer
Maxim
Datasheet

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8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
ELECTRICAL CHARACTERISTICS (continued)
(AV
C
lar devices), f
unless otherwise noted. Typical values are at T
6
Note 1: For the MAX1304/MAX1305/MAX1306, V
Note 2: All channel performance is guaranteed by correlation to a single channel test.
Note 3: The analog input resistance is terminated to an internal bias point (Figure 5). Calculate the analog input current using:
Note 4: Throughput rate is given per channel. Throughput rate is a function of clock frequency (f
Note 5: The REF input resistance is terminated to an internal +2.5V bias point (Figure 2). Calculate the REF input current using:
Note 6: The REF
Note 7: All analog inputs are driven with a -0.4dBFS 500kHz sine wave.
Note 8: Shutdown current is measured with the analog input floating. The large amplitude of the maximum shutdown current speci-
Note 9: CONVST must remain low for at least the acquisition period. The maximum acquisition time is limited by internal capacitor droop.
Note 10: CS to WR and CS to RD are internally AND together. Setup and hold times do not apply.
Note 11: Minimum CLK frequency is limited only by the internal T/H droop rate. Limit the time between the rising edge of CONVST
Input-Data Setup Time
Input-Data Hold Time
External CLK Period
External CLK High Period
External CLK Low Period
External Clock Frequency
Internal Clock Frequency
CONVST High to CLK Edge
REF-
DD
_______________________________________________________________________________________
= 0.1µF, C
= +5V, DV
MAX1312/MAX1313/MAX1314, V
for V
put rate is specified with f
Data Throughput section for more information.
for V
I
for V
fication is due to automated test equipment limitations.
and the falling edge of EOLC to a maximum of 1ms.
I
I
REFMS
REF
CH
PARAMETER
_
CLK
CH
REF
REFMS
=
=
REF+-to-REF-
=
within the input voltage range.
MS
DD
V
within the input voltage range.
= 16.67MHz 50% duty cycle, INTCLK/EXTCLK = AGND (external clock), SHDN = DGND, T
V
REF
V
CH
input resistance is terminated to an internal +2.5V bias point (Figure 2). Calculate the REF
within the input voltage range.
= +3V, AGND = DGND = 0, V
REFMS
R
REF
R
− 2 5 .
_
R
CH
REFMS
V
_
− 2 5 .
= 2.2µF || 0.1µF, C
V
BIAS
CLK
V
= 16.67MHz and the internal clock throughput rate is specified with f
SYMBOL
t
t
t
t
t
CLKH
CNTC
t
CLKL
f
IN
f
DTW
WTD
CLK
CLK
INT
= -10V to +10V.
A
COM
= +25°C. See Figures 3 and 4.)
IN
Figure 6
Figure 6
Figures 8, 9
Logic sensitive to rising edges,
Figures 8, 9
Logic sensitive to rising edges,
Figures 8, 9
(Note 11)
Figures 8, 9
REF
= 0 to +5V. For the MAX1308/MAX1309/MAX1310, V
= 2.2µF || 0.1µF, C
= V
REFMS
CONDITIONS
= +2.5V (external reference), C
MSV
= 2.2µF || 0.1µF (unipolar devices), MSV = AGND (bipo-
0.05
MIN
CLK
0.1
10
10
20
20
20
REF
). The external clock through-
= C
IN
TYP
MS
= -5V to +5V. For the
15
CLK
REFMS
input current using:
= 15MHz. See the
A
= 0.1µF, C
10.00
= T
MAX
20
MIN
to T
UNITS
MHz
MHz
REF+
ns
ns
µs
ns
ns
ns
MAX
=
,

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