MAX1421 Maxim, MAX1421 Datasheet - Page 12

• Manufacturer Part Number: MAX1421
• Description: 12-Bit / 40Msps / +3.3V / Low-Power ADC with Internal Reference
• Manufacturer: Maxim

Figure 4 shows a simplified model of the clock input cir-
cuit. This circuit consists of two 10kΩ resistors to bias
the common-mode level of each input. This circuit may
be used to AC-couple the system clock signal to the
MAX1421 clock input.
With OE high, the digital outputs enter a high-imped-
ance state. If OE is held low with PD high, the outputs
are latched at the last value prior to the power-down. All
data outputs, D0 (LSB) through D11 (MSB), are
TTL/CMOS-logic compatible. There is a seven clock-
12-Bit, 40Msps, +3.3V, Low-Power ADC
with Internal Reference
Table 1. MAX1421 Output Code for
Differential Inputs
Figure 4. Simplified Clock Input Circuit
12
* V
Output Enable ( O O E E ), Power-Down (PD), and
INPUT VOLTAGE*
-V
-V
V
V
REF
DIFFERENTIAL
REF
REF
-V
V
REF
REF
______________________________________________________________________________________
REF
REF
= V
× 2047/2048
× 2046/2048
× 2046/2048
× 2047/2048
AGND
× 1/2048
× 1/2048
REFP
0
INP
INN
CLK
CLK
A
- V
VDD
REFN
+FULL SCALE -
+FULL SCALE -
DIFFERENTIAL
-FULL SCALE +
-FULL SCALE
Bipolar Zero
+ 1 LSB
- 1 LSB
INPUT
1 LSB
1LSB
2LSB
Output Data (D0–D11)
10kΩ
10kΩ
ADC
10kΩ
10kΩ
1111 1111 1111
1111 1111 1110
1000 0000 0001
1000 0000 0000
0111 1111 1111
0000 0000 0001
0000 0000 0000
MAX1421
D11–D0
OFFSET
BINARY
cycle latency between any particular sample and its
valid output data. The output coding is in offset binary
format (Table 1).
The capacitive load on the digital outputs D0 through
D11 should be kept as low as possible (≤10pF), to
avoid large digital currents that could feed back into
the analog portion of the MAX1421, thereby degrading
its dynamic performance. The use of digital buffers
(e.g., 74LVCH16244) on the digital outputs of the ADC
can further isolate the digital outputs from heavy capac-
itive loads. To further improve the dynamic perfor-
mance of the MAX1421, add small-series resistors of
100Ω to the digital output paths, close to the ADC.
Figure 5 displays the timing relationship between out-
put enable and data output.
Figure 6 depicts the relationship between the clock
input, analog input, and data output. The MAX1421
samples at the rising edge of CLK (falling edge of CLK)
and output data is valid seven clock cycles (latency)
later. Figure 6 also displays the relationship between
the input clock parameters and the valid output data.
Figure 7 depicts a typical application circuit containing
a single-ended to differential converter. The internal ref-
erence provides an AV
shifting purposes. The input is buffered and then split to
a voltage follower and inverter. A lowpass filter at the
input suppresses some of the wideband noise associat-
ed with high-speed op amps. Select the R
values to optimize the filter performance and to suit a
particular application. For the application in Figure 7, a
R
vent ringing and oscillation. The 22pF C
acts as a small bypassing capacitor.
Connecting C
dynamic performance.
Figure 5. Output Enable Timing
ISO
DATA D11–D0
of 50Ω is placed before the capacitive load to pre-
OUTPUT
OE
IN
HIGH-Z
Applications Information
from INN to INP may further improve
System Timing Requirements
t
BE
DD
/ 2 output voltage for level-
VALID DATA
IN
ISO
HIGH-Z
capacitor
and C
t
BD
IN