MAX1421 Maxim, MAX1421 Datasheet - Page 9

• Manufacturer Part Number: MAX1421
• Description: 12-Bit / 40Msps / +3.3V / Low-Power ADC with Internal Reference
• Manufacturer: Maxim

16, 19, 41,
11, 14, 15,
21, 31, 32,
20, 42, 47
22, 29, 30
1, 4, 5, 8,
9, 12, 13,
2, 3, 10,
23–28
33–38
PIN
48
17
18
39
40
43
44
45
46
6
7
D6–D11
D0–D5
NAME
AGND
DGND
REFIN
DV
AV
REFP
REFN
CML
CLK
CLK
INP
INN
_______________________________________________________________________________________
OE
PD
DD
DD
12-Bit, 40Msps, +3.3V, Low-Power ADC
Analog Ground. Connect all return paths for analog signals to AGND.
Analog Supply Voltage. For optimum performance bypass to the closest AGND with a parallel
combination of a 0.1µF and a 1nF capacitor. Connect a single 10µF and 1µF capacitor combination
between AV
Positive Analog Signal Input
Negative Analog Signal Input
Clock Frequency Input. Clock frequency input ranges from 100kHz to 40MHz.
Complementary Clock Frequency Input. This input is used for differential clock inputs. If the ADC is
driven with a single-ended clock, bypass CLK with a 0.1µF capacitor to AGND.
Digital Supply Voltage. For optimum performance bypass, to the closest DGND with a parallel
combination of a 0.1µF and a 1nF capacitor. Connect a single 10µF and 1µF capacitor combination
between DV
Digital Ground
Digital Data Outputs. Data bits D0 through D5, where D0 represents the LSB.
Digital Data Outputs. D6 through D11, where D11 represents the MSB.
Output Enable Input. A logic “1” on OE places the outputs D0–D11 into a high-impedance state. A
logic “0” allows for the data bits to be read from the outputs.
Shutdown Input. A logic “1” on PD places the ADC into shutdown mode.
External Reference Input. Bypass to AGND with a capacitor combination of 0.22µF in parallel with
1nF. REFIN can be biased externally to adjust reference levels and calibrate full-scale errors. To
disable the internal reference, connect REFIN to AGND.
P osi ti ve Refer ence I/O . Byp ass to AG N D w i th a cap aci tor com b i nati on of 0.22µF i n p ar al l el w i th 1nF.
W i th the i nter nal r efer ence d i sab l ed ( RE FIN = AG N D ) , RE FP shoul d b e b i ased to V
N eg ati ve Refer ence I/O . Byp ass to AG N D w i th a cap aci tor com b i nati on of 0.22µF i n p ar al l el w i th 1nF.
W i th the i nter nal r efer ence d i sab l ed ( RE FIN = AG N D ) , RE FN shoul d b e b i ased to V
Common-Mode Level Input. Bypass to AGND with a capacitor combination of 0.22µF in parallel
with 1nF. With the internal reference disabled (REFIN = AGND).
DD
DD
and AGND.
and DGND.
with Internal Reference
FUNCTION
Pin Description
C M L
C M L
+ V
- V
D IF F
D IF F
/ 2.
/ 2.
9