XR16L788 Exar Corporation, XR16L788 Datasheet - Page 25

• Manufacturer Part Number: XR16L788
• Description: High-performance 3.3V Octal Uart
• Manufacturer: Exar Corporation

XR16L788 OCTAL UART
REV. 1.1.4
Logic 1 = Reset the transmit FIFO pointers and FIFO
level counter logic (the transmit shift register is not
cleared or altered). This bit will return to a logic 0 after
resetting the FIFO.
FCR[3]: DMA Mode Select
This bit has no effect since TXRDY and RXRDY pins
are not available in this device. It is provided for lega-
cy software.
Logic 0 = Set DMA to mode 0. (default)
Logic 1 = Set DMA to mode 1.
FCR[5:4]: Transmit FIFO Trigger Select
(logic 0 = default, TX trigger level = one)
The FCTR Bits 6-7 are associated with these 2 bits by
selecting one of the four tables. The 4 user selectable
T
Line Control Register (LCR)
The Line Control Register is used to specify the asyn-
chronous data communication format. The word or
character length, the number of stop bits, and the par-
ity are selected by writing the appropriate bits in this
register.
LCR[1-0]: TX and RX Word Length Select
These two bits specify the word length to be transmit-
ted or received.
ABLE
FCTR
B
IT
0
0
1
1
-7
10: T
FCTR
B
IT
0
1
0
1
RANSMIT AND
-6
B
FCR
IT
X
0
0
1
1
0
0
1
1
0
0
1
1
-7
R
B
FCR
ECEIVE
IT
X
0
1
0
1
0
1
0
1
0
1
0
1
-6
FIFO T
B
FCR
IT
X
0
0
0
1
1
0
0
1
1
-5
RIGGER
BIT
FCR
X
0
0
1
0
1
0
1
0
1
-4
L
T
Programmable Programmable Table-D. 16C850, 16c2850,
RIGGER
EVEL
1 (default)
R
25
ECEIVE
14
16
24
28
16
56
60
4
8
8
8
S
trigger levels in 4 tables are supported for compatibili-
ty reasons. These 2 bits set the trigger level for the
transmit FIFO interrupt. The UART will issue a trans-
mit interrupt when the number of characters in the
FIFO falls below the selected trigger level, or when it
gets empty in case that the FIFO did not get filled
over the trigger level on last re-load.
shows the selections.
FCR[7:6]: Receive FIFO Trigger Select
(logic 0 = default, RX trigger level =1)
The FCTR Bits 6-7 are associated with these 2 bits.
These 2 bits are used to set the trigger level for the
receiver FIFO interrupt.
selections.
ELECTION
L
EVEL
BIT-1
0
0
1
1
T
RIGGER
1 (default)
T
RANSMIT
16
24
30
16
32
56
8
8
L
EVEL
BIT-0
0
1
0
1
Table-A. 16C550, 16C2550,
16C2552, 16C554, 16C580
compatible.
Table-B. 16C650A compatible.
Table-C. 16C654 compatible.
16C2852, 16C854, 16C864,
16C872 compatible.
Table 10
C
OMPATIBILITY
shows the complete
W
5 (default)
ORD LENGTH
Table 10
6
7
8
below