XR16L788 Exar Corporation, XR16L788 Datasheet - Page 9

• Manufacturer Part Number: XR16L788
• Description: High-performance 3.3V Octal Uart
• Manufacturer: Exar Corporation

XR16L788 OCTAL UART
REV. 1.1.4
The XR16L788 has a global interrupt source register
set that consists of 4 consecutive registers [INT0,
INT1, INT2 and INT3]. The four registers are in the
device configuration register address space.
All four registers default to logic zero (as indicated in
square braces) for no interrupt pending. All 8 channel
interrupts are enabled or disabled in each channel’s
IER register. INT0 shows individual status for each
channel while INT1, INT2 and INT3 show the details
of the source of each channel’s interrupt with its
unique 3-bit encoding.
registers in sequence for clarity. The 16-bit timer and
sleep wake-up interrupts are masked in the device
configuration registers,
terrupt is generated (if enabled) by the 788 when
awakened from sleep if all 8 channels were placed in
the sleep mode previously.
Each bit gives an indication of the channel that has
F
1.1.1 The Global Interrupt Source Registers
IGURE
B it
2
[0x00]
INT3
C h a n n e l-7
B it
1
4. T
B it
0
HE
INT3 Register
G
B it
2
[0x00]
LOBAL
INT2
C h a n n e l-6
B it
1
Figure 4
TIMERCNTL and SLEEP.
I
B it
0
NTERRUPT
B it
2
[0x00]
C h a n n e l-5
INT1
shows the 4 interrupt
B it
1
R
EGISTERS
B it
0
B it
2
C h a n n e l-4
[0x00]
INT0
INT0, INT1, INT2 and INT3
B it
1
, INT0, INT1, INT2
An in-
Interrupt Registers,
INT2 Register
B it
0
B it
9
2
C h a n n e l-3
requested for service. For example, bit-0 represents
channel 0 and bit-7 indicates channel 7. Logic one in-
dicates the channel N [7:0] has called for service. The
interrupt bit clears after reading the appropriate regis-
ter of the interrupting UART channel register (ISR,
LSR and MSR). See Table 9 for interrupt clearing de-
tails.
INT3, INT2 and INT1 provide a 24-bit (3 bits per
channel) encoded interrupt indicator. Table 3 shows
the 3 bit encoding and their priority order. The 16-bit
Timer time-out interrupt will show up only as a chan-
nel 0 interrupt. For other channels, interrupt 7 is re-
served.
.
INT0 C
INT1, INT2
B it
1
C h -7
B it-7
B it
0
HANNEL
AND
C h -6
B it-6
In d ivid u a l U A R T C h a n n e l In te rru p t S ta tu s
B it
2
C h a n n e l-2
AND
INT3
C h -7
B it-7
B it
1
C h -5
B it-5
I
NTERRUPT
INT3 I
C h -6
B it-6
B it
0
IN T0 Register
C h -4
B it-4
C h -5
B it-5
B it
NTERRUPT
2
C h a n n e l-1
INT0 Register
C h -4
B it-4
INT1 Register
B it
I
C h -3
B it-3
1
NDICATOR
B it-3
C h -
B it
3
0
B it-2
C h -2
S
OURCE
C h -
B it-2
B it
2
2
:
C h a n n e l-0
C h -1 C h -0
B it-1
C h -1
B it-1
B it
1
L
OCATOR
B it-0
B it
0
C h -0
B it-0