XR18W750 ON Semiconductor, XR18W750 Datasheet - Page 18

• Manufacturer Part Number: XR18W750
• Manufacturer: ON Semiconductor

XR18W750
WIRELESS UART CONTROLLER
The internal registers of the UART are selected by address lines A2-A0 in the parallel mode. In the serial
mode, the UART registers are not accessible via these address lines. The 8051 microprocessor does not
access the enhanced UART in the parallel mode. The complete register set is shown on
4.0 UART INTERNAL REGISTERS
A2 A1 A0
A
1 X X
0 0 0
0 0 0
0 0 1
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
1 1 1
1 1 1
0 0 0
0 0 1
0 0 1
0 1 0
DDRESS
RHR - Receive Holding Register
THR - Transmit Holding Register
DLL - Divisor LSB
DLM - Divisor MSB
DREV - Device Revision Code
DVID - Device Identification Code
IER - Interrupt Enable Register
ISR - Interrupt Status Register
FCR - FIFO Control Register
LCR - Line Control Register
MCR - Modem Control Register
LSR - Line Status Register
MSR - Modem Status Register
SPR - Scratch Pad Register
FLVL - RX/TX FIFO Level Counter Register
EMSR - Enhanced Mode Select Register
TRG - RX/TX FIFO Trigger Level Register
FC - RX/TX FIFO Level Counter Register
FCTR - Feature Control Register
EFR - Enhanced Function Register
Rsrvd
T
ABLE
16C550 C
7: UART INTERNAL REGISTERS
R
EGISTER
E
NHANCED
OMPATIBLE
18
R
EGISTERS
R
EGISTERS
R
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Write-only
Write-only
Write-only
Write-only
EAD
/W
RITE
LCR ≠ 0xBF, FCTR[6] = 0
LCR ≠ 0xBF, FCTR[6] = 1
LCR[7] = 1, LCR ≠ 0xBF
LCR[7] = 1, LCR ≠ 0xBF
Table 7
DLL, DLM = 0x00,
LCR = 0xBF
LCR ≠ 0xBF
LCR ≠ 0xBF
C
LCR[7] = 0
LCR[7] = 0
OMMENTS
and
REV. 1.0.0
Table
8.