MAX148 Maxim, MAX148 Datasheet - Page 8

• Manufacturer Part Number: MAX148
• Description: +2.7V to +5.25V / Low-Power / 8-Channel / Serial 10-Bit ADCs
• Manufacturer: Maxim

The MAX148/MAX149 analog-to-digital converters
(ADCs) use a successive-approximation conversion
technique and input track/hold (T/H) circuitry to convert
an analog signal to a 10-bit digital output. A flexible seri-
al interface provides easy interface to microprocessors
(µPs). Figure 3 is a block diagram of the MAX148/
MAX149.
The sampling architecture of the ADC’s analog com-
parator is illustrated in the equivalent input circuit
(Figure 4). In single-ended mode, IN+ is internally
switched to CH0–CH7, and IN- is switched to COM. In
differential mode, IN+ and IN- are selected from the fol-
lowing pairs: CH0/CH1, CH2/CH3, CH4/CH5, and
CH6/CH7. Configure the channels with Tables 2 and 3.
In differential mode, IN- and IN+ are internally switched
to either of the analog inputs. This configuration is
pseudo-differential to the effect that only the signal at IN+
is sampled. The return side (IN-) must remain stable within
±0.5LSB (±0.1LSB for best results) with respect to AGND
during a conversion. To accomplish this, connect a 0.1µF
capacitor from IN- (the selected analog input) to AGND.
During the acquisition interval, the channel selected
as the positive input (IN+) charges capacitor C
The acquisition interval spans three SCLK cycles and
ends on the falling SCLK edge after the last bit of the
input control word has been entered. At the end of the
+2.7V to +5.25V, Low-Power, 8-Channel,
Serial 10-Bit ADCs
Figure 3. Block Diagram
8
_______________Detailed Description
_______________________________________________________________________________________
REFADJ
SHDN
SCLK
COM
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
DIN
VREF
CS
12
11
18
19
17
10
1
2
3
4
5
6
7
8
9
*A 2.00 (MAX148)
REGISTER
ANALOG
INPUT
INPUT
SHIFT
MUX
REFERENCE
(MAX149)
+1.21V
CONTROL
LOGIC
Pseudo-Differential Input
T/H
20k
A
+2.500V
IN
2.06*
CLOCK
10+2-BIT
CLOCK
REF
ADC
SAR
INT
OUT
MAX148
MAX149
REGISTER
OUTPUT
SHIFT
20
14
13
15
16
DOUT
SSTRB
V
DGND
AGND
DD
HOLD
.
acquisition interval, the T/H switch opens, retaining
charge on C
The conversion interval begins with the input multiplexer
switching C
negative input (IN-). In single-ended mode, IN- is simply
COM. This unbalances node ZERO at the comparator’s
input. The capacitive DAC adjusts during the remainder
of the conversion cycle to restore node ZERO to 0V
within the limits of 10-bit resolution. This action is equiv-
alent to transferring a 16pF x [(V
from C
which in turn forms a digital representation of the analog
input signal.
The T/H enters its tracking mode on the falling clock
edge after the fifth bit of the 8-bit control word has been
shifted in. It enters its hold mode on the falling clock
edge after the eighth bit of the control word has been
shifted in. If the converter is set up for single-ended
inputs, IN- is connected to COM, and the converter
samples the “+” input. If the converter is set up for dif-
ferential inputs, IN- connects to the “-” input, and the
difference of
conversion, the positive input connects back to IN+,
and C
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens, and more time must be
Figure 4. Equivalent Input Circuit
SINGLE-ENDED MODE: IN+ = CH0–CH7, IN- = COM.
DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS OF
COM
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
HOLD
HOLD
VREF
INPUT
MUX
charges to the input signal.
HOLD
HOLD
to the binary-weighted capacitive DAC,
|
IN+ - IN-
CAPACITIVE DAC
C
CH0/CH1, CH2/CH3, CH4/CH5, AND CH6/CH7.
SWITCH
–
C
16pF
as a sample of the signal at IN+.
from the positive input (IN+) to the
HOLD
TRACK
SWITCH
+
|
T/H
is sampled. At the end of the
R
9k
IN
HOLD
ZERO
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
IN- CHANNEL.
IN
COMPARATOR
+
) - (V
Track/Hold
IN
-)] charge