MAX148 Maxim, MAX148 Datasheet - Page 9

• Manufacturer Part Number: MAX148
• Description: +2.7V to +5.25V / Low-Power / 8-Channel / Serial 10-Bit ADCs
• Manufacturer: Maxim

allowed between conversions. The acquisition time,
t
the signal, and is also the minimum time needed for the
signal to be acquired. It is calculated by the following
equation:
where R
input signal, and t
that source impedances below 4kΩ do not significantly
affect the ADC’s AC performance.
Higher source impedances can be used if a 0.01µF
capacitor is connected to the individual analog inputs.
Note that the input capacitor forms an RC filter with the
input source impedance, limiting the ADC’s signal
bandwidth.
The ADC’s input tracking circuitry has a 2.25MHz
small-signal bandwidth, so it is possible to digitize
high-speed transient events and measure periodic sig-
nals with bandwidths exceeding the ADC’s sampling
rate by using undersampling techniques. To avoid
high-frequency signals being aliased into the frequency
band of interest, anti-alias filtering is recommended.
Figure 5. Quick-Look Circuit
ACQ
, is the maximum time the device takes to acquire
OPTIONAL FOR MAX149,
REQUIRED FOR MAX148
IN
MAX872
+3V
= 9kΩ, R
COMP
V
t
OUT
ACQ
ANALOG
_______________________________________________________________________________________
+2.500V
* FULL-SCALE ANALOG INPUT, CONVERSION RESULT = $FFF (HEX)
= 7 x (R
ACQ
INPUT
0V TO
1000pF
+2.7V to +5.25V, Low-Power, 8-Channel,
S
= the source impedance of the
0.01µF
is never less than 1.5µs. Note
S
+3V
+ R
2.5V
C1
0.1µF
IN
CH7
REFADJ
VREF
Input Bandwidth
) x 16pF
MAX148
MAX149
SSTRB
DGND
AGND
DOUT
SHDN
SCLK
COM
V
DIN
CS
DD
N.C.
+3V
Internal protection diodes, which clamp the analog input
to V
from AGND - 0.3V to V
However, for accurate conversions near full scale, the
inputs must not exceed V
lower than AGND by 50mV.
If the analog input exceeds 50mV beyond the sup-
plies, do not forward bias the protection diodes of
off channels over 2mA.
To quickly evaluate the MAX148/MAX149’s analog perfor-
mance, use the circuit of Figure 5. The MAX148/MAX149
require a control byte to be written to DIN before each
conversion. Tying DIN to +3V feeds in control bytes of
$FF (HEX), which trigger single-ended unipolar conver-
sions on CH7 in external clock mode without powering
down between conversions. In external clock mode, the
SSTRB output pulses high for one clock period before
the most significant bit of the conversion result is shift-
ed out of DOUT. Varying the analog input to CH7 will
alter the sequence of bits from DOUT. A total of 15
clock cycles is required per conversion. All transitions
of the SSTRB and DOUT outputs occur on the falling
edge of SCLK.
DD
0.1µF
and AGND, allow the channel input pins to swing
OSCILLATOR
+3V
Serial 10-Bit ADCs
2MHz
CH1
Analog Input Protection
DD
DD
CH2
OSCILLOSCOPE
+ 0.3V without damage.
by more than 50mV or be
CH3
Quick Look
CH4
SSTRB
SCLK
DOUT*
9