ATA6823 ATMEL Corporation, ATA6823 Datasheet - Page 11

• Manufacturer Part Number: ATA6823
• Description: H-bridge Motor Driver
• Manufacturer: ATMEL Corporation

5.6.1
Figure 5-4.
5.6.2
4856E–AUTO–07/07
Transmit Mode
TXD Dominant Time-out Function
(input to transmitting Node)
(output of receiving Node 1)
(output of receiving Node 2)
TXD
RXD
RXD
V
(Transceiver
supply
of transmitting
node)
S
Definition of Bus Timing Parameters
TH
TH
TH
TH
During transmission, the data at the pin TX will be transferred to the bus driver to generate a bus
signal on pin LIN.
To minimize the electromagnetic emission of the bus line, the bus driver has an integrated slew
rate control and wave-shaping unit. Transmission will be interrupted in the following cases:
The recessive BUS level is generated from the integrated 30 k pull-up resistor in series with an
active diode. This diode prevents the reverse current of VBUS during differential voltage
between VSUP and BUS (V
No additional termination resistor is necessary to use the ATA6823 in LIN slave nodes. If this IC
is used for LIN master nodes, it is necessary that the BUS pin be terminated via an external 1 k
resistor in series with a diode to VBAT.
The TXD input has an internal pull-down resistor. An internal timer prevents the bus line from
being driven permanently in dominant state. If TXD is forced low longer than t
pin LIN will be switched off to recessive mode. To reset this mode switch TXD to high (> 10 µs)
before switching LIN to dominant again.
• Thermal shutdown active or overtemperature LIN active
• Sleep mode
Rec(max)
Dom(max)
Rec(min)
Dom(min)
t
Bit
t
rx_pdf(1)
LIN Bus Signal
t
t
Bus_dom(min)
Bus_dom(max)
BUS
> V
SUP
).
t
Bit
t
rx_pdr(2)
t
Bus_rec(min)
t
Bus_rec(max)
t
rx_pdr(1)
ATA6823 [Preliminary]
t
Bit
Thresholds of
receiving node 1
Thresholds of
receiving node 2
t
rx_pdf(2)
dom
> 18.4 ms, the
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