ATA8741 ATMEL Corporation, ATA8741 Datasheet - Page 9

• Manufacturer Part Number: ATA8741
• Manufacturer: ATMEL Corporation

3.4
3.4.1
3.4.2
4. Microcontroller Block
9140B–INDCO–07/09
CLK Output
Clock Pulse Take-over
Output Matching and Power Setting
Using C
tances on each side of the crystal of C
crystal of C
tion of ±21.5 kHz with worst case tolerances of ±16.25 kHz to ±28.01 kHz.
An output CLK signal is provided for the integrated AVR. The delivered signal is CMOS compat-
ible if the load capacitance is lower than 10 pF.
The clock of the crystal oscillator can be used for clocking the microcontroller. Atmel
microcontroller starts with an integrated RC-oscillator to switch on the RF TX with ENABLE = H,
and after 3 ms assumes the clock signal of the transmission IC, so that the message can be sent
with crystal accuracy.
The output power is set by the load impedance of the antenna. The maximum output power is
achieved with a load impedance of Z
to V
The delivered current pulse of the power amplifier is 9 mA and the maximum output power is
delivered to a resistive load of 400 if the 1.0 pF output capacitance of the power amplifier is
compensated by the load impedance.
An optimum load impedance of:
Z
8 dBm.
The load impedance is defined as the impedance seen from the RF TX’s ANT1, ANT2 into the
matching network. This large signal load impedance should not be confused with the small sig-
nal input impedance delivered as input characteristic of RF amplifiers and measured from the
application into the IC instead of from the IC into the application for a power amplifier.
Less output power is achieved by lowering the real parallel part of 400 where the parallel imag-
inary part should be kept constant.
Output power measurement can be done using the circuit shown in
that the component values must be changed to compensate for the individual board parasitics
until the RF TX has the right load impedance Z
of the cable used to measure the output power must be calibrated out.
More detailed information about the microcontroller block can be found in the appendix.
Load
S
= 400 || j/(2
to deliver the DC current.
4
= 8.2 pF ±5%, C
0
= 3.2 pF ±10% and a crystal with C
1.0 pF) = (255 + j192) is achieved for the maximum output power of
5
= 10 pF ±5%, a switch port with C
Load,opt
Stray1
= (255 + j192) . There must be a low resistive path
= C
Load,opt
Stray2
M
= 13 fF ±10%, results in a typical FSK devia-
= 1 pF ±10%, a parallel capacitance of the
= (255 + j192) . In addition, the damping
Switch
Figure 8-4 on page
= 3 pF ±10%, stray capaci-
ATA8741
16. Note
®
’s AVR
9