MAX17036 Maxim Integrated Products, MAX17036 Datasheet - Page 24

• Manufacturer Part Number: MAX17036
• Description: (MAX17030 / MAX17036) 1/2/3-Phase Quick-PWM IMVP-6.5 VID Controllers
• Manufacturer: Maxim Integrated Products

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1/2/3-Phase Quick-PWM
IMVP-6.5 VID Controllers
off-time expires. The on-time for each phase is based
on the input voltage to FB ratio (i.e., follows the master
on-time), but reduced by 33% in a 3-phase configura-
tion, and not reduced in a 2-phase configuration. This
maximizes the total inductor current slew rate.
After the phase-overlap mode ends, the controller auto-
matically begins with the next phase. For example, if
phase 2 provided the last on-time pulse before overlap
operation began, the controller starts switching with
phase 3 when overlap operation ends.
The nominal no-load output voltage (V
defined by the selected voltage reference (VID DAC)
plus the remote ground-sense adjustment (V
defined in the following equation:
where V
MAX17030/MAX17036 slew the target voltage from
ground to the preset boot voltage. Table 3 is the operating
mode truth table.
Table 3. Operating Mode Truth Table
* Multiphase operation = All enabled phases active.
24
Rising
SHDN
GND
High
High
High
______________________________________________________________________________________
DAC
DPRSLPVR
INPUTS
Nominal Output Voltage Selection
V
High
is the selected VID voltage. On startup, the
Low
Low
TARGET
X
X
=
High
Low
V
PSI
X
X
X
FB
=
V
Nominal R
Nominal R
Nominal R
(N-1)-Phase Forced-PWM
Multiphase Forced-PWM
1-Phase Pulse Skipping
DAC
1/4 R
Multiphase Pulse
OPERATION*
+
TIME
Disabled
Skipping
V
PHASE
GNDS
TIME
TIME
TIME
Slew Rate
Slew Rate
Slew Rate
Slew Rate
TARGET
GNDS
) as
) is
Low-Power Shutdown Mode. DL1 and DL2 forced low, and the
controller is disabled. The supply current drops to 1µA (max).
Startup/Boot. When
MAX17036 begin the startup sequence. Once the REF is above
1.84V, the controller enables the PWM controller and ramps the
output voltage up to the boot voltage. See Figure 9.
Full Power. The no-load output voltage is determined by the selected
VID DAC code (D0–D6, Table 4).
Intermediate Power. The no-load output voltage is determined by the
selected VID DAC code (D0–D6, Table 4). When
the MAX17030/MAX17036 immediately disable phase 3, PWM3 is
three-state, and
Deeper Sleep Mode. The no-load output voltage is determined by the
selected VID DAC code (D0–D6, Table 4). When DPRSLPVR is pulled
high, the MAX17030/MAX17036 immediately enter 1-phase pulse-
skipping operation allowing automatic PWM/PFM switchover under
light loads. The PWRGD and
DH2 and DL2 are pulled low, PWM3 is three-state and
The digital-to-analog converter (DAC) programs the out-
put voltage using the D0–D6 inputs. D0–D6 are low-volt-
age (1.0V) logic inputs, designed to interface directly with
the CPU. Do not leave D0–D6 unconnected. Changing
D0–D6 initiates a transition to a new output-voltage level.
Change D0–D6 together, avoiding greater than 20ns
skew between bits. Otherwise, incorrect DAC readings
might cause a partial transition to the wrong voltage level
followed by the intended transition to the correct voltage
level, lengthening the overall transition time. The available
DAC codes and resulting output voltages are compatible
with the IMVP-6.5 (Table 4) specifications.
VID = 1111111 is defined as an OFF code. When the
OFF code is set, the MAX17030/MAX17036 go through
the same shutdown sequence as though SHDN has
been pulled low—output discharged to zero, CLKEN
high, and PWRGD low. Only the IC supply currents
remain at the operating levels rather than the shutdown
level. When exiting from the OFF code, the MAX17030/
MAX17036 go through the boot sequence, similar to the
sequence when SHDN is first pulled high.
is low.
OPERATING MODE
is pulled high, the MAX17030/
upper thresholds are blanked.
DAC Inputs (D0–D6)
is pulled low,
OFF Code
is low.