MAX3634 Maxim Integrated Products, MAX3634 Datasheet - Page 3

• Manufacturer Part Number: MAX3634
• Description: 622Mbps/1244Mbps Burst-Mode Clock Phase Aligner
• Manufacturer: Maxim Integrated Products

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ELECTRICAL CHARACTERISTICS (continued)
(V
Note 1: PECL output must have external termination of 50Ω to V
Note 2: AC parameters are guaranteed by design and characterization.
Note 3: From start of PON burst, 101010101010 preamble sequence.
Note 4: BER, acquisition time requirements are met with 100mV
Note 5: Measured with 20ps
Note 6: Jitter tolerance refers to the variation in phase between REFCLK and SDI after acquisition.
Figure 1. Definition of Clock-to-Q and Q-to-Clock Delay
(V
Serial Data Output Clock-to-Q
Delay (Figure 1)
Serial Data Output Q-to-Clock
Delay (Figure 1)
RATESEL Input High
RATESEL Input Low
RATESEL Input Current
(SCLK+) - (SCLK-)
CC
CC
SDO
(SDO+) - (SDO-)
SDI
= +3.0V to +3.6V, T
= +3.3V and T
INPUT AND OUTPUT EYE DIAGRAMS
622Mbps/1244Mbps Burst-Mode Clock Phase
PARAMETER
1.244Gbps
A
200ps/div
_______________________________________________________________________________________
= +25°C, unless otherwise noted)
A
= -40°C to +85°C. Typical values are at V
RMS
t
CLK-Q
input random jitter (1.244Mbps), 30ps
Aligner for GPON OLT Applications
SYMBOL
t
t
CLK-Q
Q-CLK
V
V
IH
IL
t
Q-CLK
SDO
SDI
622Mbps (Notes 1, 2)
1244Mbps (Notes 1, 2)
622Mbps (Notes 1, 2)
1244Mbps (Notes 1, 2)
V
IN
INPUT AND OUTPUT EYE DIAGRAMS
= 0V or V
CC
CONDITIONS
622Mbps
P-P
CC
400ps/div
- 2V (Thevenin equivalent).
sinusoidal noise on V
CC
Typical Operating Characteristics
RMS
= +3.3V, T
(622Mbps)
A
= +25°C, unless otherwise noted.)
CC
, 0 < f
LOCK
SDO
RST
SDI
-100
MIN
500
250
500
250
2
NOISE
BURST CAPTURE AT 1.244Gbps
≤ 10MHz.
TYP
1ns/div
+100
MAX
0.8
UNITS
ps
ps
µA
V
V
3