MAX3634 Maxim Integrated Products, MAX3634 Datasheet - Page 6

• Manufacturer Part Number: MAX3634
• Description: 622Mbps/1244Mbps Burst-Mode Clock Phase Aligner
• Manufacturer: Maxim Integrated Products

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The LVPECL serial data input, SDI±, and burst-mode
reset input, RST±, provide 200mV
RST± input rise and fall times (20% to 80%) must not
exceed 200ps. LVPECL inputs must be DC-coupled with
external termination for correct operation with burst data
(see Maxim Application Note HFAN 1.0 for termination
configuration).
After the first 12 or 13 bits of the preamble, plus 4 or 5
bits of synchronizer delay, LOCK asserts to indicate the
beginning of valid data output.
Internally, the MAX3634 requires five internal clock
cycles (8x REFCLK) to initialize itself after receiving the
622Mbps/1244Mbps Burst-Mode Clock Phase
Aligner for GPON OLT Applications
Figure 3. Clock Phase Aligner Operation Timing Diagram
6
_______________________________________________________________________________________
TO MAX3634
DATA INPUT
RESET
Applications Information
DATA VALID
GPON Burst-Mode Timing
GUARD TIME
T
DSR
P-P
Lock Detect
sensitivity. The
Input Stage
T
T
T
DSR
LR
CR
:
: CPA RESET AND ACQUISITION TIME, ≥ 19 BITS
: BURST-TO-BURST SEPARATION TIME
TIA/LA LEVEL RECOVERY TIME
TIA/LA ACQUISITION
T
LR
rest (BRST) signal. It then uses the next 8 bits of pream-
ble (10101010) to measure the phase relationship
between the reference clock and upstream data (after
the internal logic has been reset), and 3 to 5 bits later
begins outputting data. The time interval from BRST to
the end of the preamble must be no less than 18 bits
long. If the 8 bits of preamble that it uses to measure
phase have been excessive pulse-width distortion, the
phase measurement is in error.
The active edge of the reset input (BRST) must arrive at
the MAX3634 after the TIA has finished its level recovery,
but no sooner than 18 bits prior to the end of the (repeat-
ing 10 pattern) preamble, in order to provide adequate
time for the MAX3634 to initialize, measure the phase,
and load the output pipelines. This timing is shown in
Figure 3.
CPA RESET
(5 BITS)
CPA ACQUISITION
(12 OR 13 BITS)
T
CR
OUTPUT DATA
VALID