MAX3748 Maxim, MAX3748 Datasheet - Page 7

• Manufacturer Part Number: MAX3748
• Description: Compact 155Mbps to 3.2Gbps Limiting Amplifier
• Manufacturer: Maxim

The MAX3748/MAX3748A is susceptible to DC offsets
in the signal path because it has high gain. In commu-
nication systems using NRZ data with a 50% duty
cycle, pulse-width distortion present in the signal or
generated in the transimpedance amplifier appears as
an input offset and is reduced by the offset correction
loop. For Gigabit Ethernet and Fibre Channel applica-
tions, no capacitor is required. For SONET applications,
C
mines the lower 3dB frequency of the data path.
The MAX3748/MAX3748A limiting amplifier’s CML out-
put provides high tolerance to impedance mismatches
and inductive connectors. The output current is approx-
imately 18mA. The output is disabled by connecting the
DISABLE pin to V
DISABLE pin, the outputs OUT+ and OUT- are at a stat-
ic voltage (squelch) whenever the input signal level
drops below the LOS threshold. The output buffer can
be AC- or DC-coupled to the load (Figure 4).
The MAX3748/MAX3748A is equipped with an LOS cir-
cuitry, which indicates when the input signal is below a
programmable threshold, set by resistor R
pin (see Typical Operating Characteristics for appropri-
ate resistor sizing). An averaging peak-power detector
compares the input signal amplitude with this threshold
and feeds the signal detect information to the LOS out-
put, which is open collector. Two control voltages,
V
Figure 2. LOS Deassert Threshold Set 1dB Below the Minimum
by Receiver Sensitivity (for Selected R
_______________________________________________________________________________________________________
ASSERT
AZ
0V
V
IN
= 0.1µF is recommended. This capacitor deter-
1dB
6dB
and V
POWER-DETECT WINDOW
DEASSERT
MAX DEASSERT LEVEL
MIN DEASSERT LEVEL
CC
SIGNAL ON
. If the LOS pin is connected to the
Loss-of-Signal Indicator
Offset Correction Loop
, define the LOS assert and
CML Output Buffer
Power-Detect and
TH
)
SIGNAL OFF
TH
Compact 155Mbps to 3.2Gbps
TIME
at the TH
deassert levels. To prevent LOS chatter in the region of
the programmed threshold, approximately 2dB of hys-
teresis is built into the LOS assert/deassert function.
Once asserted, LOS is not deasserted until the input
amplitude rises to the required level (V
(Figure 5).
External resistor R
the Assert/Deassert Levels vs. R
Operating Characteristics to select the appropriate
resistor.
Figure 3. CML Input Buffer
Figure 4. CML Output Buffer
IN+
IN-
DISABLE
DATA
0.25pF
0.25pF
STRUCTURES
DISABLE
ESD
Q3
Program the LOS Assert Threshold
Limiting Amplifier
Q4
18mA
TH
programs the LOS threshold. See
DISABLE
50Ω
50Ω
Q1
Design Procedure
V
V
CC
CC
50Ω
TH
Q2
18mA
50Ω
graph in the Typical
75kΩ
DEASSERT
STRUCTURES
OUT+
OUT-
ESD
7
)