MAX5066 Maxim Integrated Products, MAX5066 Datasheet - Page 18

• Manufacturer Part Number: MAX5066
• Description: Synchronous Buck Controller
• Manufacturer: Maxim Integrated Products

worst-case RMS current occurs when only one con-
troller section is operating. The controller section with
the highest output power needs to be used in determin-
ing the maximum input RMS ripple current requirement.
Increasing the output current drawn from the other out-
of-phase controller section results in reducing the input
ripple current. A low-ESR input capacitor that can han-
dle the maximum input RMS ripple current of one chan-
nel must be used. The maximum RMS capacitor ripple
current is given by:
where I
V
C
wastes power from the input and heats up the capaci-
tor. Reducing the ESR is important to maintain a high
overall efficiency and in reducing the heating of the
capacitors.
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
Table 1. High-Side MOSFET Losses
18
Conduction Loss
Gate Drive Loss
Switching Loss
Output Loss
OUT
IN
is C5 in Figure 6. The ESR of the input capacitors
______________________________________________________________________________________
LOSS
is the output voltage of the same regulator and
MAX
I
CIN RMS
(
is the full load current of the regulator.
)
Losses associated with MOSFET on-time and
on-resistance. I
and duty cycle.
Losses associated with charging and
discharging the gate capacitance of the
MOSFET every cycle. Use the MOSFET’s (Q
specification.
Losses during the drain voltage and drain
current transitions for every switching cycle.
Losses occur only during the Q
time period and not during the initial Q
period. The initial Q
gate voltage from zero to V
R
resistance and R
resistance of the high-side MOSFET (Q
Q
Losses associated with Q
occur every cycle when the high-side MOSFET
turns on. The losses are caused by both
MOSFETs but are dissipated in the high-side
MOSFET.
≈
DH
GS2
I
MAX
is the high-side MOSFET driver’s on-
are found in the MOSFET data sheet).
V
OUT IN
RMS
(
GATE
DESCRIPTION
V
V
IN
GS1
is a function of load current
−
is the internal gate
V
period is the rise in the
OUT
OSS
TH.
)
of the MOSFET
GS2
and Q
GS1
GD
GD
and
G
)
The worst-case peak-to-peak inductor ripple current,
the allowable peak-to-peak output ripple voltage, and
the maximum deviation of the output voltage during
step loads determine the capacitance and the ESR
requirements for the output capacitors. The output rip-
ple can be approximated as the inductor current ripple
multiplied by the output capacitor’s ESR (R
The peak-to-peak inductor current ripple is given by:
During a load step, the allowable deviation of the out-
put voltage during the fast transient load dictates the
output capacitance and ESR. The output capacitors
supply the load step until the controller responds with a
greater duty cycle. The response time (t
depends on the closed-loop bandwidth of the regula-
tor. The resistive drop across the capacitor’s ESR and
capacitor discharge causes a voltage drop during a
P
P
where I
P
P
where I
GATEDRIVE
SWITCH
OUTPUT
CONDUCTION
GATE
RMS
=
=
V
Q
∆I
IN
=
≈
SEGMENT LOSS
OSS HS
=
L
V
×
=
2 (
DD
=
I
V
LOAD
I
×
(
RMS
OUT
V
V
IN
OUT
×
R
L f
)
Q
DH
×
2
2
+
G
V
×
×
(
×
Q
DD
SW
1
f
Output Capacitors
I
+
×
SW
R
LOAD
−
OSS LS
R
f
DS ON
D
SW
GATE
)
×
(
(
(
Q
)
)
GS
)
×
I
GATE
V
2
IN
RESPONSE
+
ESR_OUT
×
Q
f
GD
SW
)
).
)