AT91M43300 ATMEL Corporation, AT91M43300 Datasheet - Page 4

• Manufacturer Part Number: AT91M43300
• Description: At91arm(r) Thumb(r) Microcontrollers
• Manufacturer: ATMEL Corporation

Architectural Overview
The AT91M43300 architecture consists of two main buses,
the Advanced System Bus (ASB) and the Advanced
Peripheral Bus (APB). The ASB is designed for maximum
performance. It interfaces the processor with the on-chip
32-bit memories and the external memories and devices by
means of the External Bus Interface (EBI). The APB is
designed for accesses to on-chip peripherals and is opti-
mized for low power consumption. The AMBA Bridge pro-
vides an interface between the ASB and the APB.
An on-chip Peripheral Data Controller (PDC) transfers data
between the on-chip USARTs/SPI and the on- and off-chip
memories without processor intervention. Most importantly,
the PDC removes the processor interrupt handling over-
head and significantly reduces the number of clock cycles
required for a data transfer. It can transfer up to 64K contig-
uous bytes without reprogramming the starting address. As
a result, the performance of the microcontroller is
increased and the power consumption reduced.
The AT91M43300 peripherals are designed to be easily
programmable with a minimum number of instructions.
Each peripheral has a 16K-byte address space allocated in
the upper 3M bytes of the 4G byte address space. Except
for the interrupt controller, the peripheral base address is
the lowest address of its memory space. The peripheral
register set is composed of control, mode, data, status and
interrupt registers.
To maximize the efficiency of bit manipulation, frequently-
written registers are mapped into three memory locations.
The first address is used to set the individual register bits,
the second resets the bits and the third address reads the
value stored in the register. A bit can be set or reset by writ-
ing a one to the corresponding position at the appropriate
address. Writing a zero has no effect. Individual bits can
thus be modified without having to use costly read-modify-
write and complex bit manipulation instructions.
All of the external signals of the on-chip peripherals are
under the control of the Parallel I/O controller. The PIO
controller can be programmed to insert an input filter on
each pin or generate an interrupt on a signal change. After
reset, the user must carefully program the PIO Controller in
order to define which peripheral signals are connected with
off-chip logic.
4
AT91M43300
The ARM7TDMI processor operates in little-endian mode
in the AT91M43300 microcontroller. The processor’s inter-
nal architecture and the ARM and Thumb instruction sets
are described in the ARM7TDMI datasheet. The memory
map and the on-chip peripherals are described in the
datasheet entitled “AT91M63200 Datasheet” (Literature
No. 1028). Electrical characteristics for the AT91M43300
are documented in the datasheet “AT91M63200 Electrical
and Mechanical Characteristics” (Literature No. 1090).
The ARM standard In-Circuit Emulation debug interface is
supported via the ICE port of the AT91M43300 via the
JTAG/ICE port when JTAGSEL is low. IEEE JTAG bound-
ary scan is supported via the JTAG/ICE port when JTAG-
SEL is high.
PDC: Peripheral Data Controller
The AT91M43300 has an 8-channel PDC dedicated to the
three on-chip USARTs and to the SPI. One PDC channel is
connected to the receiving channel and one to the transmit-
ting channel of each peripheral.
The user interface of a PDC channel is integrated in the
memory space of each USART channel and in the memory
space of the SPI. It contains a 32-bit address pointer regis-
ter and a 16-bit count register. When the programmed data
is transferred, an end-of-transfer interrupt is generated by
the corresponding peripheral. See the USART section and
the SPI section for more details on PDC operation and pro-
gramming.
Power Supplies
The AT91M43300 has two kinds of power supply pins:
•
•
This allows core power consumption to be reduced by sup-
plying it with a lower voltage than the I/O lines. The
VDDCORE pins must never be powered at a voltage
greater than the supply voltage applied to the VDDIO pins.
Typical supported voltage combinations are shown in the
following table:
VDDCORE
VDDIO
VDDCORE pins, which power the chip core
VDDIO pins, which power the I/O lines
Pins
3.0V or 3.3V
5.0V
Typical Supply Voltages
3.0V or 3.3V
3.0V or 3.3V
3.0V or 3.3V
2.0V