AD1835 Analog Devices, AD1835 Datasheet - Page 13

• Manufacturer Part Number: AD1835
• Description: 2 ADC, 8DAC 96 Khz, 24-Bit Sigma Delta Codec
• Manufacturer: Analog Devices

The DAC serial data input mode defaults to I
Bits 5, 6, and 7 in DAC Control Register 1, the mode can be
changed to RJ, DSP, LJ, Packed Mode 1, or Packed Mode 2.
The word width defaults to 24 bits but can be changed by
reprogramming Bits 3 and 4 in DAC Control Register 1.
Packed Modes
The AD1835 has a packed mode that allows a DSP or other
controller to write to all DACs and read all ADCs using one
input data pin and one output data pin. Packed Mode 256
refers to the number of BCLKs in each frame. The LRCLK is
low while data from a left channel DAC or ADC is on the data
pin and high while data from a right channel DAC or ADC is
on the data pin. DAC data is applied on the DSDATA1 pin
and ADC data is available on the ASDATA pin. Figures 7–10
show the timing for the packed mode. Packed mode is only avail-
able for 48 kHz and when the ADC is set as a master (M/S = 0).
Auxiliary (TDM) Mode
A special auxiliary mode is provided to allow three external
stereo ADCs to be interfaced to the AD1835 to provide 8-
in/8-out operation. In addition, this mode supports glueless
REV. PrA
SDATA
SDATA
SDATA
SDATA
LRCLK
LRCLK
LRCLK
LRCLK
BCLK
BCLK
BCLK
BCLK
NOTES
1. DSP MODE DOES NOT IDENTIFY CHANNEL
2. LRCLK NORMALLY OPERATES AT f
3. BCLK FREQUENCY IS NORMALLY 64
MSB
MSB
MSB
MSB
PRELIMINARY TECHNICAL DATA
LEFT CHANNEL
LEFT CHANNEL
LEFT CHANNEL
S
RIGHT-JUSTIFIED MODE – SELECT NUMBER OF BITS PER CHANNEL
EXCEPT FOR DSP MODE WHICH IS 2
LRCLK BUT MAY BE OPERATED IN BURST MODE
LEFT-JUSTIFIED MODE – 16 BITS TO 24 BITS PER CHANNEL
2
LSB
S. By changing
1
DSP MODE – 16 BITS TO 24 BITS PER CHANNEL
2
S MODE – 16 BITS TO 24 BITS PER CHANNEL
Figure 4. Stereo Serial Modes
LSB
LSB
LSB
–13–
1/f
S
interface to a single SHARC DSP serial port, allowing a
SHARC DSP to access all eight channels of analog I/O. In this
special mode, many pins are redefined; see Table II for a list of
redefined pins.
The auxiliary and the TDM interfaces are independently config-
urable to operate as masters or slaves. When the auxiliary
interface is set as a master, by programming the Aux Mode bit
in ADC Control Register II, the AUXLRCLK and AUXBCLK
are generated by the AD1835. When the auxiliary interface is
set as a slave, the AUXLRCLK and AUXBCLK need to be
generated by an external ADC as shown in Figure 13.
The TDM interface can be set to operate as a master or slave by
connecting the M/S pin to DGND or ODVDD, respectively. In
master mode, the FSTDM and BCLK signals are outputs and
generated by the AD1835. In slave mode, the FSTDM and
BCLK are inputs and should be generated by the SHARC.
Slave mode operation is available for 48 kHz and 96 kHz opera-
tion (based on a 12.288 MHz or 24.576 MHz MCLK) and
master mode operation is available for 48 kHz only.
f
MSB
S
MSB
MSB
MSB
RIGHT CHANNEL
RIGHT CHANNEL
RIGHT CHANNEL
LSB
LSB
LSB
AD1835
LSB