AD1953 Analog Devices, AD1953 Datasheet - Page 31

• Manufacturer Part Number: AD1953
• Description: SigmaDSP Digital Audio Processor
• Manufacturer: Analog Devices

For the DSP serial port mode, LRCLK must pulse high for at
least one bit clock period before the MSB of the left channel is
valid, and LRCLK must pulse HIGH again for at least one bit
clock period before the MSB of the right channel is valid. Data
is sampled on the falling edge of BCLK. The DSP serial port
mode can be used with any word length up to 24 bits. In this
mode, it is the responsibility of the DSP to ensure that the left
data is transmitted with the first LRCLK pulse, and that syn-
chronism is maintained from that point forward.
The TDM data capture output mode is shown in Figure 20.
Using this mode allows six channels of serial data to be sent to
an external DAC, allowing the potential for nine total audio
channels. The frame clock is low for the first 128 BCLKs (the
first three data channels), and is then high for the final 128
BCLKs. Each data slot, which is 32 BCLK periods wide, con-
tains one data-word in an I
by one BCLK period. In this format, data is valid on the rising
edge of the BCLK.
DIGITAL CONTROL PIN
Mute
The AD1953 offers two methods of muting the analog output.
By asserting the MUTE signal high, the left, right, and sub
channels are muted. As an alternative, the user can assert the
mute bit in the serial control register high. The AD1953 has
been designed to minimize pops and clicks when muting and
unmuting the device by automatically ramping the gain up or
down. When the device is unmuted, the volume returns to the
value set in the volume register.
ANALOG OUTPUT SECTION
Figure 21 shows the block diagram of the analog output section.
A series of current sources is controlled by a digital Σ-∆ modulator.
Depending on the digital code from the modulator, each current
source is connected to the summing junction of either a positive
I-to-V converter or a negative I-to-V converter. Two extra current
sources that push instead of pull are added to set the midscale
common-mode voltage.
REV. 0
LRMUXO/
BMUXO/
DMUXO/
TDMBC
TDMFS
TDMO
Figure 20. TDM Data Capture Output Format
32BCLKs 32BCLKs 32BCLKs
SLOT 0
SLOT 1
MSB
SLOT 2
256BCLKs
2
MSB-1
S-like format, with the MSB delayed
MSB-2
32BCLKs 32BCLKs
SLOT 3
SLOT 4
LRCLK
BCLK
DATA
32BCLKs
SLOT 5
–31–
All current sources are derived from the VREF input pin. The
gain of the AD1953 is directly proportional to the magnitude of
the current sources, and therefore the gain of the AD1953 is
proportional to the voltage on the VREF pin. With VREF set to
2.5 V, the gain of the AD1953 is set to provide signal swings of
2 V rms differential (1 V rms from each pin). This is the recom-
mended operating condition.
When the AD1953 is used to drive an audio power amplifier
and the compression feature is being used, the VREF voltage
should be derived by dividing down the supply of the amplifier.
This sets a fixed relationship between the digital signal level
(which is the only information available to the digital compressor)
and the full-scale output of the amplifier (just prior to the onset
of clipping). For example, if the amplifier power supply drops
by 10%, the VREF input to the amplifier will also drop by 10%,
which will reduce the analog output signal swing by 10%. The
compressor will therefore be effective in preventing clipping
regardless of any variation in amplifier supply voltage.
Since the VREF input effectively multiplies the signal, care must
be taken to ensure that no ac signals appear on this pin. This
can be accomplished by using a large decoupling capacitor in
the VREF external resistive divider circuit. If the VREF signal is
derived by dividing the 5 V analog supply, the time constant of
the divider must effectively filter any noise on the supply. If the
VREF signal is derived from an unregulated power-amplifier
supply, the time constant must be longer, as the ripple on the
amplifier supply voltage will presumably be greater than in the
case of the 5 V supply.
The AD1953 should be used with an external third-order filter
on each output channel. The circuits shown in Figures 22, 23,
and 24 combine a third-order filter and a single-ended-to-
differential converter in the same circuit. The values used in the
main channel (Figure 22) are for a 100 kHz Bessel filter, and
those used in the subwoofer channel (Figure 23) result in a
10 kHz Bessel filter. The lower frequency filter is used on the
subwoofer output because there is no digital interpolation filter
used in the subwoofer signal path. When calculating the resistor
values for the filter, it is important to take into account the
output resistance of the AD1953, which is nominally 60 Ω.
For best distortion performance, 1% resistors should be used.
The reason for this is that the single-ended performance of the
AD1953 is about 80 dB. The degree to which the single-ended
distortion cancels in the final output is determined by the com-
mon-mode rejection of the external analog filter, which in turn
depends on the tolerance of the components used in the filter.
OUT+
FROM DIGITAL
TOR (DIG_IN)
Figure 21. Internal DAC Analog Architecture
- MODULA-
I
REF
+ DIG_IN
I
REF
SWITCHED CURRENT
BIAS
SOURCES
VREF
IN
I
REF
I
REF
– DIG_IN
AD1953
OUT–