AD1954 Analog Devices, AD1954 Datasheet - Page 31

• Manufacturer Part Number: AD1954
• Description: SigmaDSP Digital Audio Processor
• Manufacturer: Analog Devices

Sub Biquad 2 output
Sub Biquad 3 output
Sub Biquad 4 output
Sub Biquad 5 output
Sub Biquad 6 output
Sub Delay Output
Sub RMS Biquad Output
Sub RMS Output (dB)
Sub Compressor Gain (Linear)
Sub Channel Output
SERIAL DATA INPUT PORT
The AD1954’s flexible serial data input port accepts data in
two’s complement, MSB-first format. The left channel data
field always precedes the right channel data field. The serial
mode is set by using mode select bits in the SPI Control Regis-
ter. In all modes except for the right-justified mode, the serial
port will accept an arbitrary number of bits up to a limit of 24
(extra bits will not cause an error, but they will be truncated
internally). In the right-justified mode, SPI Control Register bits
are used to set the wordlength to 16, 20, or 24 bits. The default on
power-up is 24-bit mode. Proper operation of the right-justified
mode requires that there be exactly 64 BCLKS per audio frame.
Serial Data Input Modes
Figure 19 shows the serial input modes. For the left-justified
mode, LRCLK is HI for the left channel, and LO for the right
channel. Data is sampled on the rising edge of BCLK. The MSB
is left-justified to an LRCLK transition, with no MSB delay. The
left-justified mode can accept any wordlength up to 24 bits.
LRCLK
SDATA
LRCLK
SDATA
LRCLK
SDATA
LRCLK
SDATA
BCLK
BCLK
BCLK
BCLK
NOTES
1. DSP MODE DOESN’T IDENTIFY CHANNEL
2. LRCLK NORMALLY OPERATES AT
3. BCLK FREQUENCY IS NORMALLY 64
MSB
MSB
MSB
PRELIMINARY TECHNICAL DATA
MSB
LEFT CHANNEL
LEFT CHANNEL
424
433
442
451
460
511
471
489
495
511
f
S
EXCEPT DSP MODE WHICH IS 2
RIGHT JUSTIFIED MODE – SELECT NUMBER OF BITS PER CHANNEL
LRCLK BUT MAY BE OPERATED IN BURST MODE
LEFT JUSTIFIED MODE – 16 TO 24 BITS PER CHANNEL
LSB
DSP MODE – 16 TO 24 BITS PER CHANNEL
I
2
S MODE – 16 TO 24 BITS PER CHANNEL
LSB
LSB
LSB
In I
right channel. Data is valid on the rising edge of BCLK. The
MSB is left-justified to an LRCLK transition but with a single
BCLK period delay. The I
number of bits up to 24.
In right-justified mode, LRCLK is HI for the left channel, LO
for the right channel. Data is sampled on the rising edge of BCLK.
The start of data is delayed from the LRCLK edge by 16, 12, or
8 BCLKS intervals, depending on the selected wordlength. The
default wordlength is 24 bits; other wordlengths are set by writing
to bits <1:0> of Control Register 1. In right-justified mode, it is
assumed that there are 64 BCLKS per frame.
f
S
1/
Mult_out
Mult_out
Mult_out
Mult_out
Mult_out
Mult_out
Mult_out
DB_OUT
MCI
Mult_out
MSB
f
S
2
S mode. LRCLK is LO for the left channel, and HI for the
MSB
MSB
MSB
RIGHT CHANNEL
RIGHT CHANNEL
2
S mode can be used to accept any
LSB
1.23, clipped
1.23, clipped
1.23, clipped
1.23, clipped
1.23, clipped
1.23, clipped
1.23, clipped
1.23, clipped
24-bit positive binary, bit 19
corresponds to a 3 dB change
2.22, 2 LSBs = 0
LSB
LSB
AD1954
LSB