AD1955 Analog Devices, AD1955 Datasheet - Page 5

• Manufacturer Part Number: AD1955
• Description: High Performance, Multibit Sigma-delta DAC With Sacd Playback
• Manufacturer: Analog Devices

PIN FUNCTION DESCRIPTIONS
Rev. PrF
Pin
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1
2
3
4
5
6
7
8
9
Output
Output
Output
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
I/O
I/O
Pin Name
DVDD
EF_WCLK/LRCLK
EF_BCLK/BCLK
EF_LDATA/SDATA
EF_RDATA
DSD_SCLK
DSD_LDATA
DSD_RDATA
DSD_PHASE
AGND
IOUTR+
IOUTR-
FILTR
IREF
AVDD
FILTB
IOUTL-
IOUTL+
AGND
ZEROR
ZEROL
MUTE
PD/RST
CDATA
CLATCH
CCLK
MCLK
DGND
Description
Digital Power Supply Connected to Digital 5V supply.
Word Clock in External Filter mode.
Left/Right Clock input for input data in PCM mode.
Bit Clock input in External Filter mode. Bit Clock input for input data in PCM mode.
8fs or 4fs L-ch Data input in External filter mode. Data should be MSB first two’s
complement format. In the PCM mode, serial input, MSB first, containing two
channels(left and right) of 16 to 24bit two’s complement 1fs data.
8fs or 4fs R-ch Data input in External filter mode. Data should be MSB first two’s
complement format. Not used in PCM mode
Shift clock input for DSD data. This clock should be 64x44.1kHz, 2.8224MHz or
128x44.1kHz, 5.6448MHz in normal mode or 128x44.1kHz, 5.6448MHz or
256x44.1kHz, 11.2896MHz in phase mode.
DSD Left channel data input
DSD Right channel data input
DSD phase reference signal. This clock should be 64x44.1kHz, 2.8224MHz. If not
used this pin should be connected Low.
Analog Ground
Right Channel Positive analog output.
Right Channel Negative analog output.
Voltage Reference Filter Capacitor Connection. Bypass and decouple the voltage
reference with parallel 10uF and 0.1uF capacitors to AGND
Connection point for external bias resistor.
Analog power supply Connected to Analog 5V supply
Filter Capacitor Connection with parallel 10uF and 0.1uF capacitors to AGND
Left Channel Negative analog output.
Left Channel Positive analog output.
Analog Ground
Right Channel Zero Flag Output. This pin goes high when the right channel has no
signal input or the DSD mute pattern is detected.
Left Channel Zero Flag Output. This pin goes high when the left channel has no signal
input or the DSD mute pattern is detected.
Mute. Assert HI to mute both stereo analog outputs. Deassert LO for normal
operation.
Power down/Reset. The AD1955 is placed in a reset state and the digital circuitry is
powered down when this pin is held LO. The AD1955 is reset on the rising edge of
this signal. The serial control port registers are reset to the default values. Connect HI
for normal operation.
Serial control input, MSB first, containing 16 bits of unsigned data. Used for
specifying control information and channel-specific attenuation.
Latch Input for control data.
Control Clock input for control data. Control input data must be valid on the rising
edge of CCLK. CCLK may be continuous or gated.
Master Clock Input. Connect to an external clock source.
Digital Ground
-5-
AD1955