AD1980 Analog Devices, AD1980 Datasheet - Page 23

• Manufacturer Part Number: AD1980
• Description: AD1980 AC'97 SoundMAX® Codec W/spdif W/eq
• Manufacturer: Analog Devices

All registers not shown, and bits containing an X are assumed to be reserved.
Register 60h is a read/write register that controls the Equalizer functionality and data setup. This register also contains the Biquad and Coefficient Address pointer,
which is used in conjunction with the EQ Data Register (78h) to set up the equalizer coefficients. The reset default disables the Equalizer function until the coeffi-
cients can be properly set up by the software and sets the Symmetry Bit to allow equal coefficients for the left and right channels.
BCA[5,0]
CHS
SYM
EQM
REV. 0
Reg
No. Name
60h EQ CTRL EQM
Biquad and Coefficient Address Pointer:
D15
biquad 0
biquad 0
biquad 0
biquad 0
biquad 0
biquad 1
biquad 1
biquad 1
biquad 1
biquad 1
biquad 2
biquad 2
biquad 2
biquad 2
biquad 2
biquad 3
biquad 3
biquad 3
biquad 3
biquad 3
biquad 4
biquad 4
biquad 4
biquad 4
biquad 4
biquad 5
biquad 5
biquad 5
biquad 5
biquad 5
biquad 6
biquad 6
biquad 6
biquad 6
biquad 6
Channel Select.
CHS = 0 selects left channel coefficients data block.
CHS = 1 selects right channel coefficients data block.
Symmetry.
When set to “1,” this bit indicates that the left and right channel coefficients are equal. This shortens the coeffi-
cients’ setup sequence since only the left channel coefficients need to be addressed and set up. (The right channel
coefficients are fetched from the left channel memory.)
Equalizer Mute.
When set to “1,” this bit disables the equalizer function (allows all data pass through). The reset default sets this bit
to “1,” disabling the equalizer function until the biquad coefficients can be properly set.
D14
X
coef a0
coef a1
coef a2
coef b1
coef b2
coef a0
coef a1
coef a2
coef b1
coef b2
coef a0
coef a1
coef a2
coef b1
coef b2
coef a0
coef a1
coef a2
coef b1
coef b2
coef a0
coef a1
coef a2
coef b1
coef b2
coef a0
coef a1
coef a2
coef b1
coef b2
coef a0
coef a1
coef a2
coef b1
coef b2
D13
X
BCA[5,0] = 011011
BCA[5,0] = 011010
BCA[5,0] = 011001
BCA[5,0] = 100000
BCA[5,0] = 011111
BCA[5,0] = 011110
BCA[5,0] = 100101
BCA[5,0] = 100100
BCA[5,0] = 100011
BCA[5,0] = 101010
BCA[5,0] = 101001
BCA[5,0] = 101000
BCA[5,0] = 101111
BCA[5,0] = 101110
BCA[5,0] = 101101
BCA[5,0] = 110100
BCA[5,0] = 110011
BCA[5,0] = 110010
BCA[5,0] = 111001
BCA[5,0] = 111000
BCA[5,0] = 110111
BCA[5,0] = 011101
BCA[5,0] = 011100
BCA[5,0] = 100010
BCA[5,0] = 100001
BCA[5,0] = 100111
BCA[5,0] = 100110
BCA[5,0] = 101100
BCA[5,0] = 101011
BCA[5,0] = 110001
BCA[5,0] = 110000
BCA[5,0] = 110110
BCA[5,0] = 110101
BCA[5,0] = 111011
BCA[5,0] = 111010
D12
X
D11
X
EQ Control Register (Index 60h)
D10
X
D9
X
–23–
D8
X
D7
SYM CHS
D6
D5
BCA5 BCA4 BCA3 BCA2 BCA1 BCA0 8080h
D4
D3
D2
D1
AD1980
D0
Default