nRF24E2 Nordic VLSI, nRF24E2 Datasheet - Page 58

• Manufacturer Part Number: nRF24E2
• Description: Single Chip RF Transmitter + MCU + ADC NRF2402 2.4GHz RF Transmitter
• Manufacturer: Nordic VLSI

PRODUCT SPECIFICATION
Instruction cycles in the nRF24E2 are four clock cycles in length, as opposed to
twelve clock cycles per instruction cycle in the standard 8051. This translates to a 3X
improvement in execution time for most instructions. However, some instructions
require a different number of instruction cycles on the nRF24E2 than they do on the
standard 8051. In the standard 8051, all instructions except for MUL and DIV take
one or two instruction cycles to complete. In the nRF24E2 architecture, instructions
can take between one and five instruction cycles to complete. For example, in the
standard 8051, the instructions MOVX A, @DPTR and MOV direct, direct each take
two instruction cycles (twenty-four clock cycles) to execute. In the nRF24E2
architecture, MOVX A, @DPTR takes two instruction cycles (eight clock cycles) and
MOV direct, direct takes three instruction cycles (twelve clock cycles). Both
instructions execute faster on the nRF24E2 than they do on the standard 8051, but
require different numbers of clock cycles.
For timing of real-time events, use the numbers of instruction cycles from Table 10-3
to Table 10-8 to calculate the timing of software loops. The bytes column of these
table indicates the number of memory accesses (bytes) needed to execute the
instruction. In most cases, the number of bytes is equal to the number of instruction
cycles required to complete the instruction. However, as indicated in Table 10-3, there
are some instructions (for example, DIV and MUL) that require a greater number of
instruction cycles than memory accesses.By default, the nRF24E2 timer/counters run
at twelve clock cycles per increment so that timer-based events have the same timing
as with the standard 8051. The timers can be configured to run at four clock cycles per
increment to take advantage of the higher speed of the nRF24E2.
The nRF24E2 employs dual data pointers to accelerate data memory block moves.
The standard 8051 data pointer (DPTR) is a 16-bit value used to address external data
RAM or peripherals. The nRF24E2 maintains the standard data pointer as DPTR0 at
SFR locations 0x82 and 0x83. It is not necessary to modify code to use DPTR0. The
nRF24E2 adds a second data pointer (DPTR1) at SFR locations 0x84 and 0x85. The
SEL bit in the DPTR Select register, DPS (SFR 0x86), selects the active pointer.
When SEL = 0, instructions that use the DPTR will use DPL0 and DPH0. When SEL
= 1, instructions that use the DPTR will use DPL1 and DPH1. SEL is the bit 0 of SFR
location 0x86. No other bits of SFR location 0x86 are used. All DPTR-related
instructions use the currently selected data pointer. To switch the active pointer, toggle
the SEL bit. The fastest way to do so is to use the increment instruction (INC DPS).
This requires only one instruction to switch from a source address to a destination
address, saving application code from having to save source and destination addresses
when doing a block move.
Using dual data pointers provides significantly increased efficiency when moving
large blocks of data.
The SFR locations related to the dual data pointers are:
Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone [phone] - Fax [phone]
Revision: 1.0
- 0x82 DPL0 DPTR0 low byte
- 0x83 DPH0 DPTR0 high byte
- 0x84 DPL1 DPTR1 low byte
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August 2003