STK672-330 Sanyo Semicon Device, STK672-330 Datasheet - Page 5

• Manufacturer Part Number: STK672-330
• Description: Two-Phase Stepping Motor Driver
• Manufacturer: Sanyo Semicon Device

• Motor current peak value I
I
Vref = (R02 ÷ (R01 + R02)) 5 V (or 3.3 V)
Rs is the hybrid IC internal current detection resistor.
In the STK672-330 (and STK672-350) Rs is 0.195 Ω.
(In the STK672-340 and STK672-360, Rs is 0.14 Ω.)
Input Pin Functions (TTL input levels)
• A simple reset function is formed from D1, CO4, RO3, and RO4 in this application circuit. With the CLOCK input
• See the timing chart for the concrete details on circuit operation.
Usage Notes
• STK672-330 input signal functions and timing (Specifications common to the STK672-340, 350, and 360 as well)
OH
CLOCK
MODE
CWB
RESETB
ENABLE
held low, when the 5-V supply voltage is brought up a reset is applied if the motor output phases A and BB are driven.
If the 5-V supply voltage rise time is slow (over 50 ms), the motor output phases A and BB may not be driven. Increase
the value of the capacitor CO4 and check circuit operation again.
(All inputs have no internal pull-up resistor and are TTL level Schmitt trigger inputs.)
[RESETB and CLOCK (Input signal timing when power is first applied)]
As shown in the timing chart, a RESETB signal input is required by the driver to operate with the timing in which the
F1 gate is turned on first. The RESETB signal timing must be set up to have a width of at least 10 µs, as shown below.
The capacitor CO4, and the resistors RO3 and RO4 in the application circuit form simple reset circuit that uses the RC
time constant rising time. However, when designing the RESETB input based on V
the timing shown in figure 1.
Pin
= Vref ÷ Rs
Pin No.
10
11
12
9
8
Rise of the 5-V supply voltage
RESETB signal input
CLOCK signal
Reference clock for motor phase current switching
Excitation mode selection
Motor direction switching
System reset and A, AB, B, and BB outputs cutoff.
Applications must apply a reset signal for at least 10 µs when V
The A, AB, B, and BB outputs are turned off, and after operation is restored by
returning the ENABLE pin to the high level, operation continues with the same
excitation timing as before the low-level input.
OH
Figure 1 RESETB and CLOCK Signals Input Timing
setting
I OH
O
Function
At least 10 µs
STK672-330
At least 5 µs
DD
is first applied.
ITF02173
IH
Operates on the rising edge of the signal
Low: 2-phase excitation
High: 1-2 phase excitation
Low: CW (forward)
High: CCW (reverse)
A reset is applied by a low level
The A, AB, B, and BB outputs are turned
off by a low-level input.
levels, the application must have
Input conditions when operating
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