W90210F Winbond Electronics Corp America, W90210F Datasheet - Page 30

• Manufacturer Part Number: W90210F
• Description: Pa-risc Embedded Controller
• Manufacturer: Winbond Electronics Corp America

memory. The DMA mechanism will provide two different methods for performing DMA transfers: demand-mode
transfers and block-mode transfers. The DMAC hardware is responsible for synchronizing transfers with memory or
external devices.
input (DREQ1:0#). The DMAC acknowledges the requesting device with an acknowledge signal (DACK1:0#) when
the requesting device is accessed.
and continued until terminated or suspended. The DMA operation is started when the enable bit in the Configuration
Register is set.
8.2 DMA Controller (DMAC)
The DMAC megacell provides two DMA channels to support DMA transfers between 8-bit I/O devices and main
When the DMAC is configured for demand mode, an external device requests a DMA transfer with a request
In block mode, DMA transfers are not requested by an external device. The DMA operation is initiated by software
In programming the megacell registers, the register address is defined by the BASE register plus the offset value.
the starting address of the DMA transfer source.
starting address of the DMA transfer target.
current DMA transfer.
8.2.1 Register Description:
Source Starting Address Register (SSAR0=080, SSAR1=084)
Target Starting Address Register (TSAR0=081, TSAR1=085)
Length/Count Register (LETH0=082, LETH1=086)
The above information is the exclusive intellectual property of Winbond Electronics Corp. and shall not be disclosed, distributed or reproduced without permission from Winbond.
Interface
Bus
DMAC megacell
Figure 8.5 DMA controller
DEV address
30
TXCOUNT
MODE
SSAR
TSAR
LETH
: LETH is a read/write 32-bit register that records the counts of
: TSAR is a read/write 32-bit register that contains the
: SSAR is a read/write 32-bit register that contains
DREQ#[2]
DACK#[2]
IOR
IOW
IODATA[8]
DA[12]
CS[2]
W90210F
Version 1.4, 10/8/97