AD8116 Analog Devices, AD8116 Datasheet

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AD8116

Manufacturer Part Number
AD8116
Description
200 Mhz, 16 3 16 Buffered Video Crosspoint Switch
Manufacturer
Analog Devices
Datasheet

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PRODUCT DESCRIPTION
The AD8116 is a high speed 16 × 16 video crosspoint switch
matrix. It offers a –3 dB signal bandwidth greater than 200 MHz
and channel switch times of 60 ns with 0.1% settling. With –70 dB
of crosstalk and –105 dB of isolation (@ 5 MHz), the AD8116
is useful in many high speed applications. The differential gain
and differential phase errors of better than 0.01% and 0.01°,
respectively, along with 0.1 dB flatness out to 60 MHz make the
AD8116 ideal for video signal switching.
The AD8116 includes output buffers that can be placed into a
high impedance state for paralleling crosspoint outputs so that
off channels do not load the output bus. It operates on voltage
Patent Pending.
supplies of ± 5 V while consuming only 90 mA of idle current.
The channel switching is performed via a serial digital control
that can accommodate “daisy chaining” of several devices.
The AD8116 is packaged in a 128-lead LQFP package occupy-
ing only 0.36 square inches, and is specified over the commer-
cial temperature range of 0°C to 70°C.
16 INPUTS
UPDATE
DATA IN
RESET
CLK
CE
–1
–2
–3
–4
100k
4
3
2
1
0
200 MHz, 16
R
L
= 50
FUNCTIONAL BLOCK DIAGRAM
Video Crosspoint Switch
FLATNESS
1M
16
80-BIT SHIFT REG.
PARALLEL LATCH
5:16 DECODERS
DECODE
SWITCH
FREQUENCY – Hz
MATRIX
AD8116
80
80
256
10M
2V p-p
200mV p-p
2V p-p
OUTPUT
BUFFER
+1
+1
+1
+1
+1
+1
+1
+1
16
+1
+1
+1
+1
+1
+1
+1
+1
16 Buffered
100M
AD8116
200mV p-p
1G
0.5
0.4
0.3
0.2
0.1
–0.1
–0.2
–0.3
0
CLK
DATA OUT
UPDATE
CE
RESET
16 OUTPUTS

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AD8116 Summary of contents

Page 1

... It offers a –3 dB signal bandwidth greater than 200 MHz and channel switch times with 0.1% settling. With – crosstalk and –105 dB of isolation (@ 5 MHz), the AD8116 is useful in many high speed applications. The differential gain and differential phase errors of better than 0.01% and 0.01°, respectively, along with 0 ...

Page 2

... AD8116–SPECIFICATIONS Parameter DYNAMIC PERFORMANCE –3 dB Bandwidth Slew Rate Settling Time Gain Flatness NOISE/DISTORTION PERFORMANCE Differential Gain Error Differential Phase Error Crosstalk, All Hostile Off Isolation, Input-Output Input Voltage Noise DC PERFORMANCE Gain Gain Matching OUTPUT CHARACTERISTICS Output Offset Voltage Output Impedance ...

Page 3

... ON FALLING EDGE 3 OUT15 (D3 INCREASING TIME Table I. Logic Levels DATA OUT CLK, DATA IN, CE, UPDATE 20 µA max 0.5 V max AD8116 Limit Typ Max Unit 200 µs 16 100 ns 200 ns OUT00 (D0) ...

Page 4

... AD8116 ABSOLUTE MAXIMUM RATINGS Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Internal Power Dissipation AD8116 128-Lead Plastic LQFP (ST 3.5 W Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Short Circuit Duration . . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves Storage Temperature Range . . . . . . . . . . . . –65°C to +125°C Lead Temperature Range (Soldering 10 sec 300°C NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only ...

Page 5

... CLR Q Q CLR Q DECODE 256 SWITCH MATRIX AD8116 Operation/Comment No change in logic. The data on the DATA IN line is loaded into the serial register. The first bit clocked into the serial register appears at DATA OUT 80 clocks later. Data in the serial shift register transfers into the parallel latches that control the switch array ...

Page 6

... AD8116 Pin Name Pin Numbers INxx 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, 32 DATA IN 37, 126 CLK 36, 125 DATA OUT 35, 124 UPDATE 38, 123 RESET 39, 122 CE 40, 121 OUTyy 65, 67, 69, 71, 73, 75, 77, 79, 81, 83, 85, 87, 89, 91, 93, 95 AGND 11, 13, 15, 17, 19, ...

Page 7

... AGND 21 22 IN10 23 AGND IN11 24 AGND 25 IN12 26 AGND 27 28 IN13 29 AGND 30 IN14 AGND 31 IN15 CONNECT AD8116 128L LQFP (14mm x 14mm) TOP VIEW (Not to Scale) AD8116 96 AVCC00 95 OUT00 94 AVEE00/01 93 OUT01 92 AVCC01/02 91 OUT02 90 AVEE02/03 89 OUT03 88 AVCC03/04 87 OUT04 86 AVEE04/05 85 OUT05 84 AVCC05/06 83 OUT06 82 AVEE06/07 ...

Page 8

... AD8116 –Typical Performance Characteristics 150 0pF p-p FLATNESS –1 –2 2V p-p –3 200mV p-p –4 100k 1M 10M FREQUENCY – Hz – – 37.5 S ALL HOSTILE CROSSTALK – 632mV p-p IN –40 –50 –60 –70 ADJACENT CHANNEL –80 V –90 –100 300k 1M 10M FREQUENCY – ...

Page 9

... FREQUENCY – Hz 316 100 31.6 10 3.16 10 100 1k 10k 100k 1M FREQUENCY – Hz 10M 1M 100k 10k 1k 100 100k 1M 10M 100M FREQUENCY – Hz Typical Performance Characteristics–AD8116 1V/DIV 10mV/DIV 0 –10 –20 10M –50 –60 V –70 –80 –90 –100 –110 –120 –130 –140 – ...

Page 10

... AD8116 10M 1M 100k 10k 1k 100 30k 100k 1M 10M FREQUENCY – 200mV 150 –3 –6 –9 –12 –15 30k 100k 1M 10M FREQUENCY – 200mV IN 0 150 L 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 –0.5 30k 100k 1M FREQUENCY – Hz 100M ...

Page 11

... AD8116 is shown in Figure 4. In normal operation, the DATA OUT pin of one AD8116 is connected to the DATA IN of the next. In this way, for example, an array of eight AD8116s would be programmed with one 640-bit sequence. In this mode CE is logic low and the CLK and UPDATE pins are connected in parallel ...

Page 12

... ORing at the output to only four outputs. This will prevent an enabled output from having to drive a large number of disabled devices. Additionally, by using the lower eight outputs from each of the two Rank 2 AD8116s, a blocking 128 × 32 crosspoint array can be realized. There are, however, some drawbacks to this technique. The offset voltages of the various cascaded devices will accumulate and the bandwidth limitations of the devices will compound ...

Page 13

... Power-On Reset Most systems will want all the AD8116s the reset state (all outputs disabled) when power is applied to the system. This ensures that two outputs that are wire-ORed together will not fight each other at power up ...

Page 14

... As a crosspoint system or device grows larger, the number of theoretical crosstalk combinations and permutations can become extremely large. For example, in the case of the 16 × 16 matrix of the AD8116, we can examine the number of crosstalk terms that can be considered for a single channel, say IN00 input. IN00 is programmed to connect to one of the AD8116 outputs where the measurement can be made ...

Page 15

... In addition, the load resistor actually lowers the crosstalk com- pared to the conditions of the AD8116 outputs driving a high impedance (greater than 10 kΩ) or driving a video load (150 Ω). This is because the electric field crosstalk that dominates in the high impedance case has a phase of – ...

Page 16

... POWER SUPPLY CONNECTOR CLIP-ON TEST POINTS 0.01 F 0.01 F 0.01 F 0.01 F 113– 116– 127 119 118 120 115 AD8116JST 43–45 0. CONNECT 0 PINS 96,92,88,84 TO PINS 94,90,86,82 (AVCC) (AVEE) 97–104, 105– ...

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... AD8116 ...

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... AD8116 ...

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... AD8116 ...

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... AD8116 ...

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... AD8116 ...

Page 22

... As can be seen in Figure 17, there is extensive power supply decoupling on the evaluation board. Figure 17 shows the location of all the decoupling capacitors relative to the AD8116’s pins. Four large 10 µF capacitors are located near the evaluation board’s power supply connection terminals. ...

Page 23

... DVCC DVEE AVEE 128 127 119 1 0 (DVCC) (DVEE CONNECT 0.1 F 113 AD8116 AVCC 10 F 0.01 F ...

Page 24

... AD8116 Controlling the Evaluation Board from a PC The evaluation board include Windows-based control software and a custom cable that connects the board’s digital interface to the printer port of the PC. The wiring of this cable is shown in Figure 18. The software requires Windows 3.1 or later to operate. To install the software, insert the disk labeled “Disk #1 of 2” ...

Page 25

... AD8116 ...

Page 26

... AD8116 Metric measurements are not rounded. English measurements are rounded. 0.030 (0.75) 0.024 (0.60) 0.018 (0.45) SEATING STANDOFF 0.003 (0.08) OUTLINE DIMENSIONS Dimensions shown in millimeters and (inches). 128-Lead Plastic LQFP (ST-128A) 0.630 (16.00) BSC 0.063 (1.60) 0.551 (14.00) BSC MAX 0.488 (12.40) BSC 128 1 PLANE TOP VIEW (PINS DOWN) ...

Page 27

... Location Data Sheet changed from REV REV. B. Correction to pin number in Pin Function Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Revision History–AD8116 Page ...

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