AD823A Analog Devices, AD823A Datasheet - Page 11

• Manufacturer Part Number: AD823A
• Description: Dual, 16 Mhz, Rail-to-rail Fet Input Amplifier
• Manufacturer: Analog Devices

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THEORY OF OPERATION
This AD823 is fabricated on Analog Devices’ proprietary
complementary bipolar (CB) process that enables the construc-
tion of pnp and npn transistors with similar f
to 800 MHz region. In addition, the process also features
N-channel JFETs, which are used in the input stage of the AD823.
These process features allow the construction of high frequency,
low distortion op amps with picoampere input currents. This
design uses a differential-output input stage to maximize band-
width and headroom (see Figure 35). The smaller signal swings
required on the S1P, S1N outputs reduce the effect of nonlinear
currents due to junction capacitances and improve the distortion
performance. With this design harmonic distortion of better
than –91 dB @ 20 kHz into 600
single 5 volt supply is achieved. The complementary common-
emitter design of the output stage provides excellent load drive
without the need for emitter followers, thereby improving the
output range of the device considerably with respect to conven-
tional op amps. The AD823 can drive 20 mA with the outputs
within 0.6 V of the supply rails. The AD823 also offers out-
standing precision for a high speed op amp. Input offset voltages
V
V
V
V
INP
INN
CC
EE
J1
R42
I1
with V
R37
J6
C6
Figure 34. Pulse Response, V
Q72
Q53
OUT
T
s in the 600 MHz
R33
–10V
10V
S1P
= 4 V p-p on a
Figure 35. Simplified Schematic
Q48
V
V
BE
CC
I2
R
C
+ 0.3V
L
L
Q35
= 100k
= 50pF
5V
Q61
R43
S1N
V1
Q46
–11–
I5
I3
Q21
of 1 mV max and offset drift of 2 V/ C are achieved through
the use of Analog Devices’ advanced thin-film trimming
techniques.
A “Nested Integrator” topology is used in the AD823 (see small-
signal schematic shown in Figure 36). The output stage can be
modeled as an ideal op amp with a single-pole response and a
unity-gain frequency set by transconductance g
C2. R1 is the output resistance of the input stage; g
put transconductance. C1 and C5 provide Miller compensation
for the overall op amp. The unity gain frequency will occur at
g
where:
A0 = g
A2 = g
m
/C5. Solving the node equations for this circuit yields:
S
Q43
Q56
500ns
Q58
Q62
= 15 V, G = +1
m
m2
R44
V
g
R2 (Open Loop Gain of Output Stage)
m2
Vi
OUT
R2R1 (Open Loop Gain of Op Amp)
R28
V
B
Q55
Q49
Q60
Q52
( sR1[C1( A2 1)] 1)
Q54
I6
I4
Q18
Q59
A=1
Q44
A=1
C2
C1
A0
Q57
A=19
Q17
A=19
V
s
OUT
g
C2
m2
m2
AD823
and capacitor
m
1
is the in-