AT90RF135602 ATMEL, AT90RF135602 Datasheet - Page 13

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AT90RF135602

Manufacturer Part Number
AT90RF135602
Description
INTEGRATED 13.56 MHz CONTACTLESS READER WITH EMBEDED SOFTWARE
Manufacturer
ATMEL
Datasheet
General
SPI Setup
SPI Command/Response
Message Structure
4407A–SCR–04/05
This section describes the operation and interface protocol between the typical host
controller and the AT90RF135602 for v2.7 of software.
The AT90RF135602 always operates as a slave to the host controller device acting as
the master.
The SPI interface operation is specified by the /SS and /RESET lines as shown in the
table below.
To clarify:
The AT90RF135602 ignores SCK from the host and tri-states the MOSI and MISO lines
whilst /SS is high
As the slave, the AT90RF135602 accepts the SCK from the host and produces serial
output data from its MISO output only when /SS is low.
The MOSI input is used to receive commands and data from the host in conjunction with
the SCK clock when /SS is low.
Operation from a cold power-up and reset defaults to be in low quiescent current “Sleep
Mode” waiting for /SS to go low.
AT90RF135602 is slave.
/SS idle condition is high.
Prior to transmitting a message the /SS line is set low by the host, after the message
has been transmitted the /SS line is set back high again.
The interval between the host lowering /SS and then generating the first SCK pulse
should be a minimum of 3us.
SCK idle condition is low.
The leading edge is rising and the trailing edge falling.
In each direction data is loaded on the rising clock edge and is valid (and sampled) on
the falling clock edge.
The minimum interval between the 8
shall be 10us for status poll commands and 23us for all other commands.
The host generates the SPI clock signals to send “Command” messages to the
AT90RF135602.
The host generates the SPI clock signals to receive “Response” messages from the
AT90RF135602.
The generic message structure is independent of message direction and is transparent
to the SPI hardware interface.
/RESET
High
High
Low
Low or High
High
/SS
Low
th
SCK of a byte and the 1
SPI interface and AT90RF135602 active
Interface Mode
Sleep mode
Reserved
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st
SCK of the next byte
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