AT90RF135602 ATMEL, AT90RF135602 Datasheet - Page 20

• Manufacturer Part Number: AT90RF135602
• Description: INTEGRATED 13.56 MHz CONTACTLESS READER WITH EMBEDED SOFTWARE
• Manufacturer: ATMEL

Sleep-Mode
SPI Clock Frequency
Power On Reset, Reset &
Host In-circuit
Programming
Power On Reset (POR)
Reset
Built-In Self Test (BIST)
Mode
General
Initiation
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The AT90RF135602 will enter low quiescent current “Sleep Mode” when /SS is high and
all tag operations have been completed.
This is determined by the host micro-controller, since this is the master and hence will
generate the SCK signal.
The recommended SPI clock frequency is 115kHz.
From cold start the POR will occur followed by initialisation of the microprocessor. From
application of power the AT90RF135602 will be ready to receive an SPI command data
within 6 mS.
The active low /RESET signal from the host will cause the AT90RF135602 to enter the
reset condition. From release of this signal high the AT90RF135602 will be ready to
receive SPI command data within 6 mS.
When /RESET is held low the AT90RF135602 will enter serial programming mode. In
this mode the SPI SCK, MISO, MOSI lines may be used to upgrade the firmware.
The BIST consists of a single sequence of test stages designed as a confidence test
that the AT90RF135602 is operational and also as a basic diagnostic aid if operation
becomes impaired.
Beyond this it is not possible to perform an exhaustive test of operational performance
without the presence of a tag for functional test purposes.
The BIST mode is activated by the single byte Host SPI command 0x70.
BIST Sequence:
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The Loop around Test is designed to test the Xtal oscillator, antenna drive and demodu-
lator sections of the AT88RF135602 for connectivity and operation to a limited functional
extent.
CRC Verification of all Flash Program Memory
Integrity of all RAM Memory
Loop around Test
If this test fails, subsequent tests are not performed.
If this test fails, subsequent tests are not performed.
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4407A–SCR–04/05