AT91SAM9260 ATMEL Corporation, AT91SAM9260 Datasheet
AT91SAM9260
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AT91SAM9260 Summary of contents
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... Three External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected ™ ® ® ARM Thumb Processor ® ® Technology for Java Acceleration AT91 ARM Thumb ® Microcontrollers AT91SAM9260 Summary Preliminary NOTE: This is a summary document. The complete document is available on the Atmel website at www.atmel.com. 6221DS–ATARM–22-Sep-06 ...
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... VDDIOP1 (Peripheral I/Os) – 3.0V to 3.6V for VDDIOP0 and VDDANA (Analog-to-digital Converter) – Programmable 1.65V to 1.95V or 3.0V to 3.6V for VDDIOM (Memory I/Os) • Available in a 208-lead PQFP Green and a 217-ball LFBGA RoHS-compliant Package AT91SAM9260 Preliminary 2 ™ Compliant ® Infrared Modulation/Demodulation, Manchester Encoding/Decoding ...
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... The AT91SAM9260 is based on the integration of an ARM926EJ-S processor with fast ROM and RAM memories and a wide range of peripherals. The AT91SAM9260 embeds an Ethernet MAC, one USB Device Port, and a USB Host con- troller. It also integrates several standard peripherals, such as the USART, SPI, TWI, Timer Counters, Synchronous Serial Controller, ADC and MultiMedia Card Interface ...
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MASTER SLAVE System TST Controller FIQ AIC IRQ0-IRQ2 DBGU DRXD DTXD PDC PCK0-PCK1 PMC PLLRCA PLLA PLLB XIN OSC XOUT WDT PIT 4GPREG RC OSCSEL XIN32 OSC RTT XOUT32 PIOA SHDN SHDC 32 Kbytes WKUP PIOB VDDBU POR PIOC VDDCORE ...
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... Programmable Clock Output Shutdown, Wakeup Logic Shutdown Control Wake-up Input ICE and JTAG Test Reset Signal Test Clock Test Data In Test Data Out Test Mode Select JTAG Selection AT91SAM9260 Preliminary Active Type Level Comments Power 1.65V to 1.95V or 3.0V to3.6V Power 3.0V to 3.6V Power 1.65V to 3.6V Power 1 ...
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... NRD NWE NBS0 - NBS3 CFCE1 - CFCE2 CFOE CFWE CFIOR CFIOW CFRNW CFCS0 - CFCS1 NANDCS AT91SAM9260 Preliminary 6 Function Return Test Clock Reset/Test Microcontroller Reset Test Mode Select Boot Mode Select Debug Unit - DBGU Debug Receive Data Debug Transmit Data Advanced Interrupt Controller - AIC ...
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... USART0 Data Carrier Detect USART0 Ring Indicator Synchronous Serial Controller - SSC SSC Transmit Data SSC Receive Data SSC Transmit Clock SSC Receive Clock SSC Transmit Frame Sync SSC Receive Frame Sync AT91SAM9260 Preliminary Active Type Level Comments Output Low Output Low ...
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... ETXEN ETX0-ETX3 ETXER ERXDV ERX0-ERX3 ERXER ECRS ECOL EMDC EMDIO EF100 AT91SAM9260 Preliminary 8 Function Timer/Counter - TCx TC Channel x External Clock Input TC Channel x I/O Line A TC Channel x I/O Line B Serial Peripheral Interface - SPIx_ Master In Slave Out Master Out Slave In SPI Serial Clock SPI Peripheral Chip Select 0 ...
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... Image Sensor Interface Image Sensor Data Image Sensor Reference Clock Image Sensor Horizontal Synchro Image Sensor Vertical Synchro Image Sensor Data clock Analog to Digital Converter Analog Inputs Analog Positive Reference ADC Trigger AT91SAM9260 Preliminary Active Type Level Comments Input Output Input Input Input ...
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... PQFP Green package (0.5mm pitch) • 217-ball LFBGA RoHS-compliant package (0.8 mm ball pitch) Figure 4-1 shows the orientation of the 208-pin PQFP package. A detailed mechanical description is given in the section “AT91SAM9260 Mechanical Charac- teristics” of the product datasheet. Figure 4-1. 208-pin PQFP Package 156 ...
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... A2 149 98 NWR2/NBS2/A1 150 99 NBS0/A0 151 100 SDA10 152 101 CFIOW/NBS3/NWR3 153 102 CFIOR/NBS1/NWR1 154 103 SDCS/NCS1 155 104 CAS 156 AT91SAM9260 Preliminary Signal Name Pin RAS 157 D0 158 D1 159 D2 160 D3 161 D4 162 D5 163 D6 164 GND 165 VDDIOM 166 SDCK 167 ...
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... LFBGA Package Outline www.DataSheet4U.com AT91SAM9260 Preliminary 12 Figure 4-2 shows the orientation of the 217-ball LFBGA package. A detailed mechanical description is given in the section “AT91SAM9260 Mechanical Charac- teristics” of the product datasheet. Figure 4-2. 217-ball LFBGA Package (Top View ...
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... P8 H17 PB18 P9 J1 PC19 P10 J2 PC17 P11 J3 VDDIOM P12 J4 PC16 P13 J8 GND P14 J9 GND P15 J10 GND P16 AT91SAM9260 Preliminary Signal Name Pin Signal Name TDO P17 PB5 PB19 R1 NC TDI R2 GNDANA PB16 R3 PC29 PC24 R4 VDDANA PC20 R5 PB12 D15 R6 PB23 PC21 ...
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... Separated ground pins are provided for VDDBU, VDDPLL and VDDANA. These ground pins are respectively GNDBU, GNDOSC, GNDPLL and GNDANA. The AT91SAM9260 consumes about 500 µA of static current on VDDCORE at 25°C. This static current rises the temperature increases to 85°C. ...
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... NRST and NTRST pins can be left unconnected. The NRST and NTRST pins both integrate a permanent pull-up resistor to VDDIOP0. Its value can be found in the table “DC Characteristics” in the section “AT91SAM9260 Electrical Char- acteristics” in the product datasheet. The NRST signal is inserted in the Boundary Scan. ...
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... The SHDN pin is an output only, which is driven by the Shutdown Controller. The pin WKUP is an input-only. It can accept voltages only between 0V and VDDBU. The AT91SAM9260 slow clock can be generated either by an external 32,768 Hz crystal or the on-chip RC oscillator. Table 6-1 on page 16 defines the states for OSCSEL signal. ...
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... Boot Mode Select – Non-volatile Boot Memory can be internal or external – Selection is made by BMS pin sampled at reset • Remap Command – Allows Remapping of an Internal SRAM in Place of the Boot Non-Volatile Memory – Allows Handling of Dynamic Exception Vectors AT91SAM9260 Preliminary 17 ...
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... Master to Slave Access AT91SAM9260 Preliminary 18 The Bus Matrix of the AT91SAM9260 manages six Masters, which means that each master can perform an access concurrently with others, according the slave it accesses is available. Each Master has its own decoder that can be defined specifically for each master. In order to simplify the addressing, all the masters have the same decodings ...
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... ADC Receive Channel – SPI1 Receive Channel – SPI0 Receive Channel – SSC Receive Channel – MCI Transmit/Receive Channel • ARM926 Real-time In-circuit Emulator – Two real-time Watchpoint Units – Two Independent Registers: Debug Control Register and Debug Status Register AT91SAM9260 Preliminary 19 ...
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... AT91SAM9260 Preliminary 20 – Test Access Port Accessible through JTAG Protocol – Debug Communications Channel • Debug Unit – Two-pin UART – Debug Communication Channel Interrupt Handling – Chip ID Register • IEEE1149.1 JTAG Boundary-scan on All Digital Pins 6221DS–ATARM–22-Sep-06 ...
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... Memories Figure 8-1. AT91SAM9260 Memory Mapping Address Memory Space 0x0000 0000 Internal Memories 0x0FFF FFFF 0x1000 0000 EBI Chip Select 0 0x1FFF FFFF 0x2000 0000 EBI Chip Select 1/ SDRAMC 0x2FFF FFFF www.DataSheet4U.com 0x3000 0000 EBI Chip Select 2 0x3FFF FFFF 0x4000 0000 EBI Chip Select 3/ ...
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... Embedded Memories 8.1.1 Boot Strategies AT91SAM9260 Preliminary 22 A first level of address decoding is performed by the Bus Matrix, i.e., the implementation of the Advanced High Performance Bus (AHB) for its Master and Slave interfaces with additional features. Decoding breaks up the 4G bytes of address space into 16 banks of 256 Mbytes. The banks are directed to the EBI that associates these banks to the external chip selects EBI_NCS0 to EBI_NCS7 ...
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... External Bus Interface 6221DS–ATARM–22-Sep-06 The AT91SAM9260 matrix manages a boot memory that depends on the level on the BMS pin at reset. The internal memory area mapped between address 0x0 and 0x000F FFFF is reserved for this purpose. If BMS is detected at 1, the boot memory is the embedded ROM. ...
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... Static Memory Controller 8.2.3 SDRAM Controller AT91SAM9260 Preliminary 24 – SDRAM Controller – ECC Controller • Additional logic for NANDFlash • Full 32-bit External Data Bus • 26-bit Address Bus (up to 64MBytes linear) • chip selects, Configurable Assignment: – Static Memory Controller on NCS0 – ...
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... ECC value available in a register • Automatic Hamming Code Calculation while reading – Error Report, including error flag, correctable error flag and word address being detected erroneous – Support 8- or 16-bit NAND Flash devices with 512-, 1024-, 2048- or 4096-bytes pages AT91SAM9260 Preliminary 25 ...
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... System Controller www.DataSheet4U.com AT91SAM9260 Preliminary 26 The System Controller is a set of peripherals that allows handling of key elements of the sys- tem, such as power, resets, clocks, time, interrupts, watchdog, etc. The System Controller User Interface also embeds the registers that configure the Matrix and a set of registers for the chip configuration ...
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... Block Diagram Figure 9-1. AT91SAM9260 System Controller Block Diagram dbgu_irq www.DataSheet4U.com NRST VDDCORE VDDBU VDDBU SHDN WKUP OSC_SEL XIN32 CLOCK XOUT32 XIN XOUT PLLRCA PA0-PA31 PB0-PB31 PC0-PC31 6221DS–ATARM–22-Sep-06 System Controller irq0-irq2 Advanced fiq Interrupt periph_irq[2..24] Controller pit_irq rtt_irq wdt_irq ...
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... Reset Controller 9.3 Shutdown Controller www.DataSheet4U.com 9.4 Clock Generator AT91SAM9260 Preliminary 28 • Based on two Power-on-reset cells – One on VDDBU and one on VDDCORE • Status of the last reset – Either general reset (VDDBU rising), wake-up reset (VDDCORE rising), software reset, user reset or watchdog reset • ...
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... Slow Clock Mode, processor and peripherals running at low frequency – Standby Mode, mix of Idle and Backup Mode, peripheral running at low frequency, processor stopped waiting for an interrupt – Backup Mode, Main Power Supplies off, VDDBU powered by a battery AT91SAM9260 Preliminary Slow Clock SLCK Main Clock ...
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... Figure 9-3. AT91SAM9260 Power Management Controller Block Diagram SLCK MAINCK PLLACK PLLBCK www.DataSheet4U.com 9.6 Periodic Interval Timer 9.7 Watchdog Timer 9.8 Real-time Timer 9.9 General-purpose Back-up Registers 9.10 Advanced Interrupt Controller AT91SAM9260 Preliminary 30 Master Clock Controller Prescaler Divider /1,/2,/3,/4 /1,/2,/4,...,/64 Programmable Clock Controller SLCK Prescaler MAINCK PLLACK /1,/2,/4,...,/64 PLLBCK USB Clock Controller ...
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... Support for two PDC channels with connection to receiver and transmitter • Debug Communication Channel Support – Offers visibility of and interrupt trigger from COMMRX and COMMTX signals from the ARM Processor’s ICE Interface • Chip ID: 0x019803A0 • JTAG ID: 0x05B1303F • ARM926 TAP ID: 0x0792603F AT91SAM9260 Preliminary ® USART 31 ...
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... FFFF. Each User Peripheral is allocated 16 Kbytes of address space. A complete memory map is presented in Table 10-1 defines the Peripheral Identifiers of the AT91SAM9260. A peripheral identifier is required for the control of the peripheral interrupt with the Advanced Interrupt Controller and for the control of the peripheral clock with the Power Management Controller. Table 10-1. ...
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... IRQ2, use a dedicated Peripheral ID. However, there is no clock control associated with these peripheral IDs. The AT91SAM9260 features 3 PIO controllers (PIOA, PIOB, PIOC) that multiplex the I/O lines of the peripheral set. Each PIO Controller controls lines. Each line can be assigned to one of two peripheral functions ...
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... ADTRG PA23 TWD PA24 TWCK PA25 TCLK0 PA26 TIOA0 PA27 TIOA1 PA28 TIOA2 PA29 SCK1 (1) PA30 SCK2 (1) PA31 SCK0 Note: 1. Not available in the 208-lead PQFP package. AT91SAM9260 Preliminary 34 PIO Controller A Peripheral B Comments Reset State MCDB0 I/O MCCDB I/O I/O MCDB3 I/O MCDB2 I/O MCDB1 I/O I/O I/O I/O I/O ETX2 I/O ETX3 ...
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... ISI_D0 I/O ISI_D1 I/O ISI_D2 I/O ISI_D3 I/O ISI_D4 I/O ISI_D5 I/O ISI_D6 I/O ISI_D7 I/O ISI_PCK I/O ISI_VSYNC I/O ISI_HSYNC I/O ISI_MCK I/O AT91SAM9260 Preliminary Application Usage Power Supply Function Comments VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP0 VDDIOP0 RDY/BUSY signal for VDDIOP0 NANDFlash in ...
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... D23 PC24 D24 PC25 D25 PC26 D26 PC27 D27 PC28 D28 PC29 D29 PC30 D30 PC31 D31 Note: 1. Not available in the 208-lead PQFP package. AT91SAM9260 Preliminary 36 PIO Controller C Peripheral B Comments Reset State SCK3 AD0 I/O PCK0 AD1 I/O PCK1 AD2 I/O SPI1_NPCS3 AD3 I/O SPI1_NPCS2 ...
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... Optional Multi-drop Mode with address generation and detection – Optional Manchester Encoding • RS485 with driver control signal • ISO7816 Protocols for interfacing with smart cards – NACK handling, error counter with repetition and iteration limit AT91SAM9260 Preliminary 37 ...
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... Remote Loopback, Local Loopback, Automatic Echo The USART contains features allowing management of the Modem Signals DTR, DSR, DCD and RI. In the AT91SAM9260, only the USART0 implements these signals, named DTR0, DSR0, DCD0 and RI0. The USART1 and USART2 do not implement all the modem signals. Only RTS and CTS (RTS1 and CTS1, RTS2 and CTS2, respectively) are implemented in these USARTs for other features ...
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... Interrupt generation to signal receive and transmit completion • 28-byte transmit and 28-byte receive FIFOs • Automatic pad and CRC generation on transmitted frames • Address checking logic to recognize four 48-bit addresses • Support promiscuous mode where all valid frames are copied to memory AT91SAM9260 Preliminary 39 ...
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... Image Sensor Interface www.DataSheet4U.com 10.4.11 Analog-to-Digital Converter AT91SAM9260 Preliminary 40 • Support physical layer management through MDIO interface • ITU-R BT. 601/656 8-bit mode external interface support • Support for ITU-R BT.656-4 SAV and EAV synchronization • Vertical and horizontal resolutions up to 2048 x 2048 • ...
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... Package Drawings Figure 11-1. 208-lead TQFP Package Drawing www.DataSheet4U.com 6221DS–ATARM–22-Sep-06 AT91SAM9260 Preliminary 41 ...
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... Figure 11-2. 217-ball LFBGA Package Drawing www.DataSheet4U.com AT91SAM9260 Preliminary 42 6221DS–ATARM–22-Sep-06 ...
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... AT91SAM9260 Ordering Information Table 12-1. AT91SAM9260 Ordering Information Ordering Code AT91SAM9260-QU AT91SAM9260-CJ www.DataSheet4U.com 6221DS–ATARM–22-Sep-06 AT91SAM9260 Preliminary Package Package Type PQFP208 Green BGA217 RoHS-compliant Temperature Operating Range Industrial -40°C to 85°C 43 ...
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... In Figure 2-1 on page 4 removed TWI PDC channels. In Section 6.3 ”Reset Pins” on page In Figure 9-3 on page In Section 10.4.3 ”USART” on page AT91SAM9260 Preliminary 44 14. Section 4-1 ”Pinout for 208-pin PQFP Package” 11. and corrected supported voltage levels in 14. 10. Section 4-1 ”Pinout for 208-pin PQFP Package” 11. ...
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