MT57V256H36P Micron Semiconductor Products, Inc., MT57V256H36P Datasheet - Page 2

• Manufacturer Part Number: MT57V256H36P
• Description: 9Mb DDR SRAM 2.5V Vdd, HSTL Pipelined
• Manufacturer: Micron Semiconductor Products, Inc.

GENERAL DESCRIPTION (continued)
ideally suited for applications requiring very rapid data
transfer by operation in data-doubled mode. The device
is also ideal in applications requiring the cost benefits of
pipelined CMOS SRAMs and the reduced READ-to-WRITE
turnaround times of Late Write SRAMs.
all inputs and outputs are HSTL-compatible. The device
is ideally suited for cache, network, telecom, DSP, and
other applications that benefit from a very wide, high-
speed data bus.
sramds) for the latest data sheet.
DDR OPERATION
through high clock frequencies (achieved through pipe-
lining) and double data rate mode of operation. At slower
frequencies, the DDR SRAM requires a single NO OPERA-
TION (NOP) cycle when transitioning from a READ to a
WRITE cycle. At higher frequencies, a second NOP cycle
may be required to prevent bus contention. NOP cycles
NOTE: 1. SA0 and SA1 are advanced in linear burst order at each K and K# rising edge.
SA0, SA1, SA
256K x 36 2.5V V
MT57V256H36P_5.p65 – Rev. 5, Pub. 5/02
The SRAM operates from a +2.5V power supply, and
Please refer to Micron’s Web site
The DDR SRAM enables high performance operation
R/W#
LD#
K#
K
2. The compare width is a 16-bits. The compare is performed only if a WRITE is pending and a READ cycle is requested. If
3. The functional block diagram illustrates simplified device operation. See truth table, ball descriptions, and timing
4. CQ, CQ# do not tristate except during some JTAG test modes.
DD
the address matches, data is routed directly to the device outputs, bypassing the memory array.
diagrams for detailed information.
, HSTL, Pipelined DDR SRAM
18
36
36
E
E
E
REGISTER
REGISTER
REGISTER
ADDRESS
ADDRESS
E
E
REGISTER
REGISTER
WRITE
R/W#
INPUT
INPUT
COMPARE
18
36
(NOTE 2)
WRITE#
36
SA0''’
SA0’
SA0#’
SA0’
SA0#’
SA0’
0
1
18
CLK
36
CLK
36
36
(www.micron.com/
SA1
SA0
FUNCTIONAL BLOCK DIAGRAM
D1
D0
REGISTER
WRITE
C
BURST
LOGIC
(NOTE 1)
16
18
REGISTER
Q1
Q0
36
OE
36
SA0’
SA1’
DRIVER
WRITE
18
18
256K x 36
2.5V V
36
36
WRITE#
WRITE#
READ
128K x 72
MEMORY
2
ARRAY
SA1’-SA17’
are not required when switching from a WRITE to a
READ.
data for the WRITE are stored in registers. The write
information must be stored because the SRAM cannot
perform the last WORD WRITE to the array without con-
flicting with the READ. The data stays in this register until
the next WRITE cycle occurs. On the first WRITE cycle
after the READ(s), the stored data from the earlier WRITE
will be written into the SRAM array. This is called a
POSTED WRITE.
if that address was written in the previous cycle. During
this READ cycle, the SRAM array is bypassed, and data is
read instead from the data register storing the recently
written data. This is transparent to the user. This feature
facilitates system data coherency.
cessor, the Claymore DDR SRAM. Single data rate opera-
tion is not supported, hence no SD/DD# ball is provided.
Only bursts of four are supported. In addition to the echo
SA0''
DD
36
36
If a READ occurs after a WRITE cycle, address and
A READ can be made immediately to an address even
The DDR SRAM differs in some ways from its prede-
SENSE
AMPS
Micron Technology, Inc., reserves the right to change products or specifications without notice.
, HSTL, PIPELINED DDR SRAM
C#
C
C
36
36
CONTROL
OUTPUT
LOGIC
REGISTER
OUTPUT
36
36
SA0'''
MUX
2:1
0
1
36
36
36
OUTPUT
BUFFER
256K x 36
ZQ
E
©2002, Micron Technology, Inc.
36
DQ
CQ, CQ#