MT57V256H36P Micron Semiconductor Products, Inc., MT57V256H36P Datasheet - Page 5

• Manufacturer Part Number: MT57V256H36P
• Description: 9Mb DDR SRAM 2.5V Vdd, HSTL Pipelined
• Manufacturer: Micron Semiconductor Products, Inc.

BALL DESCRIPTIONS
256K x 36 2.5V V
MT57V256H36P_5.p65 – Rev. 5, Pub. 5/02
5N-7N, 4P, 5P,
7P, 8P, 3R-5R,
4B, 8B, 5C,
2H, 10H
7R-9R
BALL
11H
10R
11R
8A
4A
6A
6C
7C
6B
6P
6R
2R
DD
, HSTL, Pipelined DDR SRAM
SYMBOL
R/W#
TMS
TCK
V
SA0
SA1
LD#
TDI
ZQ
SA
K#
C#
K
C
REF
TYPE
Input
Input
Input
Input
Input
Input
Input
Input
Input
(continued on next page)
Synchronous Read/Write Input: When LD# is LOW, this input
Input Clock: This input clock pair registers address and control
Output Clock: This clock pair provides a user controlled means of
IEEE 1149.1 Test Inputs: JEDEC-standard 2.5V I/O levels. These balls
IEEE 1149.1 Clock Input: JEDEC-standard 2.5V I/O levels. This ball
Synchronous Address Inputs: These inputs are registered and must
meet the setup and hold times around the rising edge of K. Balls
9A, 3A, 10A, and 2A are reserved for the next higher-order address
inputs on 18, 36, 72, and 144Mb devices, respectively. SA0 and
SA1 are used as the lowest two address bits for BURST READ and
BURST WRITE operations. These inputs are ignored when device is
deselected or once BURST operation is in progress.
Synchronous Load: This input is brought LOW when a bus cycle
sequence is to be defined. This definition includes address and
read/write direction. All transactions operate on a burst of 4 data
(two clock periods of bus activity).
designates the access type (READ when R/W# is HIGH, WRITE when
R/W# is LOW) for the loaded address. R/W# must meet the setup
and hold times around the rising edge of K.
inputs on the rising edge of K, and registers data on the rising
edge of K and the rising edge of K#. K# is ideally 180 degrees out
of phase with K. All synchronous inputs must meet setup and hold
times around the clock rising edges.
tuning device output data. The rising edge of C is used as the
output timing reference for first and third output data. The rising
edge of C# is used as the output reference for second and fourth
output data. Ideally, C# is 180 degrees out of phase with C. C and
C# may be tied HIGH to force the use of K and K# as the output
reference clocks instead of having to provide C and C# clocks. If
tied HIGH, C and C# must remain HIGH and not be toggled during
device operation.
Output Impedance Matching Input: This input is used to tune the
device outputs to the system data bus impedance. DQ and CQ
output impedance are set to 0.2 x RQ, where RQ is a resistor from
this bump to ground. Alternately, this ball can be connected
directly to V
This ball cannot be connected directly to GND or left unconnected.
may be left Not Connected if the JTAG function is not used in the
circuit.
must be tied to V
HSTL Input Reference Voltage: Nominally V
reference voltage for the input buffers.
2.5V V
5
DD
Q, which enables the minimum impedance mode.
DD
SS
Micron Technology, Inc., reserves the right to change products or specifications without notice.
, HSTL, PIPELINED DDR SRAM
if the JTAG function is not used in the circuit.
DESCRIPTION
DD
Q/2. Provides a
256K x 36
©2002, Micron Technology, Inc.