MT57W1MH18J Micron Semiconductor Products, Inc., MT57W1MH18J Datasheet - Page 11

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MT57W1MH18J

Manufacturer Part Number
MT57W1MH18J
Description
18Mb Ddrii SRAM, 1.8V Vdd, Hstl, 4-Word Burst,
Manufacturer
Micron Semiconductor Products, Inc.
Datasheet
Table 6:
x 18, x 36 only
NOTE:
18Mb: 1.8V V
MT57W1MH18J_H.fm – Rev. H, Pub. 3/03
1. SA0 and SA1 are internally advanced in accordance with the burst order table. Bus cycle is terminated after burst
2. State transitions: L = (LD# = LOW); L# = (LD# = HIGH); R = (R/W# = HIGH); W = (R/W# = LOW).
3. State machine, control timing sequence is controlled by K.
count = 4.
LOAD NEW ADDRESS
FIRST ADDRESS
Count=0
DD
, HSTL, DDRIIb4 SRAM
(EXTERNAL)
X . . . X00
X . . . X01
X . . . X10
X . . . X11
Burst Address Table
L, Count=4
R
W
L, Count=4
SECOND ADDRESS
Count=Count+2
Count=Count+2
WRITE DOUBLE
(INTERNAL)
READ DOUBLE
X . . . X01
X . . . X10
X . . . X11
X . . .X00
Bus Cycle State Diagram
L#, Count=4
L#, Count=4
Figure 4:
always
Count=2
always
Count=2
11
2 MEG
L
1.8V V
THIRD ADDRESS
ADVANCE ADDRESS
ADVANCE ADDRESS
Micron Technology, Inc., reserves the right to change products or specifications without notice.
(INTERNAL)
X . . . X10
X . . . X11
X . . . X00
X . . . X01
BY TWO 1
BY TWO 1
X
8, 1 MEG
DD
, HSTL, DDRIIb4 SRAM
X
18, 512K
FOURTH ADDRESS
(INTERNAL)
X . . . X11
X . . . X00
X . . . X01
X . . . X10
POWER-UP
NOP
©2003 Micron Technology, Inc.
provided
voltage
Supply
X
36
L#

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