MT9040AN Zarlink Semiconductor, MT9040AN Datasheet - Page 12

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MT9040AN

Manufacturer Part Number
MT9040AN
Description
Description = Single Reference Frequency Selectable, 3.3V Digital PLL With Multiple Clock Outputs For Stratum 4 Applications ;; Package Type = Ssop ;; No. Of Pins = 48
Manufacturer
Zarlink Semiconductor
Datasheet

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Reset Circuit
A simple power up reset circuit with about a 50us reset low time is shown in Figure 7. Resistor R
only and limits current into the RST pin during power down conditions. The reset low time is not critical but should
be greater than 300ns.
Lock Indicator
The LOCK pin toggles at a random rate when the PLL is frequency locked to the input reference. In Figure 8 the
RC-time-constant circuit can be used to hold the high state of the LOCK pin.
Once the PLL is frequency locked to the input reference, the minimum duration of LOCK pin’s high state would be
32ms and the maximum duration of LOCK pin’s low state would not exceed 1 second. The following equations can
be used to calculate the charge and discharge times of the capacitor.
t
t
C
D
= - R
= - R C ln(V
D
t
R
C = Capacitor value (1µF)
V
Schmitt Trigger (3.0 V)
V
t
R = Resistor value (3.3 MΩ)
C = Capacitor value (1µF)
V
Schmitt Trigger (2.0 V)
V
C
D
C ln(1 – V
T+
DD
T-
DD
D
= Capacitor’s charge time
= Capacitor’s discharge time
= Dynamic resistance of the diode (100 Ω)
= Negative going threshold voltage of the
= Positive going threshold voltage of the
= 3.3 V
= 3.3 V
T-
/V
DD
T+
) = 1.65 seconds
/V
DD
) = 240 µs
Figure 7 - Power-Up Reset Circuit
MT9040
RST
Zarlink Semiconductor Inc.
MT9040
12
1kΩ
R
10kΩ
P
R
+3.3V
10nF
C
P
is for protection
Data Sheet

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