MT9040AN Zarlink Semiconductor, MT9040AN Datasheet - Page 6

• Manufacturer Part Number: MT9040AN
• Description: Description = Single Reference Frequency Selectable, 3.3V Digital PLL With Multiple Clock Outputs For Stratum 4 Applications ;; Package Type = Ssop ;; No. Of Pins = 48
• Manufacturer: Zarlink Semiconductor

The frame pulse outputs (F0o, F8o, F16o, TSP, and RSP) are generated directly from the C16 clock.
The T1 and E1 signals are generated from a common DPLL signal. Consequently, all frame pulse and clock outputs
are locked to one another for all operating states, and are also locked to the input reference in Normal Mode. See
Figures 10,11 and 12.
All frame pulse and clock outputs have limited driving capability, and should be buffered when driving high
capacitance (e.g., 30pF) loads.
Input Impairment Monitor
This circuit monitors the input signal to the DPLL for a complete loss of incoming signal, or a large frequency shift in
the incoming signal. If the input signal is outside the Impairment Monitor Capture Range the PLL automatically
changes from Normal Mode to Free Run Mode. See AC Electrical Characteristics - Performance for the Impairment
Monitor Capture Range. When the incoming signal returns to normal, the DPLL is returned to Normal Mode.
Master Clock
The MT9040 can use either a clock or crystal as the master timing source. For recommended master timing
circuits, see the Applications - Master Clock section.
Figure 4 - Output Interface Circuit Block Diagram
DPLL
From
Tapped
Tapped
Tapped
Tapped
Delay
Delay
Delay
Delay
Line
Line
Line
Line
Zarlink Semiconductor Inc.
MT9040
12MHz
16MHz
19MHz
12MHz
6
DS2 Divider
T1 Divider
E1 Divider
C19o
C1.5o
C2o
C4o
C8o
C16o
F0o
F8o
F16o
RSP
TSP
C6o
Data Sheet