MT9042 Mitel Networks Corporation, MT9042 Datasheet - Page 2

• Manufacturer Part Number: MT9042
• Description: Global Digital Trunk Synchronizer
• Manufacturer: Mitel Networks Corporation

MT9042
3-98
Pin Description
Pin #
10
11
12
1
2
3
4
5
6
7
8
9
FP8-STB Frame Pulse Output (CMOS compatible). This is an 8 kHz output framing pulse that
FP8-GCI Frame Pulse Output (CMOS compatible). This is an 8 kHz output framing pulse that
MCLKo
MCLKi
Name
TRST
SEC
C1.5
F0o
V
PRI
V
C3
DD
SS
Negative Power Supply Voltage. Nominally 0 Volts.
TIE Circuit Reset (TTL compatible). When HIGH, the time interval error correction circuit is
alternately establishing the phase difference between the PRI and SEC reference inputs,
depending upon which input is selected as input for PLL synchronization. This information is
used to generate a virtual reference for input to the PLL. When LOW, the time interval error
correction circuit is bypassed.
Secondary Reference Input (TTL compatible). This input (either 8 kHz, 1.544 MHz, or
2.048 MHz as controlled by the input frequency selection pins) is used as an alternate
reference source for PLL synchronization.
Primary Reference Input (TTL compatible). This input (either 8 kHz, 1.544 MHz, or 2.048
MHz as controlled by the input frequency selection pins) is used as the primary reference
source for PLL synchronization.
Positive Supply Voltage. Nominally +5 volts.
Master Clock Oscillator Output. This is a CMOS buffered output used for driving a 20 MHz
crystal.
Master Clock Oscillator Input. This is a CMOS input for a 20 MHz crystal or crystal
oscillator. Signals should be DC coupled to this pin.
indicates the start of the active GCI-BUS frame. The pulse width is based upon the period of
the 8.192 MHz synchronization clock.
Frame Pulse Output (CMOS compatible). This is an 8 kHz output framing pulse that
indicates the start of the active ST-BUS frame. The pulse width is based upon the period of
the 4.096 MHz synchronization clock. This is an active low signal.
indicates the start of the active ST-BUS frame. The pulse width is based upon the period of
the 8.192 MHz synchronization clock.
Clock 1.544 MHz (CMOS compatible). This ouput is a 1.544 MHz (T1) output clock locked
to the selected reference input signal.
Clock 3.088 MHz (CMOS compatible). This output is a 3.088 MHz output clock locked to
the selected reference input signal.
FP8-STB
FP8-GCI
MCLKo
MCLKi
VDD
C1.5
F0o
Figure 2 - Pin Connections
12 13 14 15 16 17 18
10
11
5
4
6
7
8
9
3 2
1
28
Description
27
19
26
25
24
23
22
21
20
RSEL
MS1
MS2
LOSS1
LOSS2
GTo
GTi
Preliminary Information