MT9042 Mitel Networks Corporation, MT9042 Datasheet - Page 7

• Manufacturer Part Number: MT9042
• Description: Global Digital Trunk Synchronizer
• Manufacturer: Mitel Networks Corporation

Preliminary Information
maximum time interval error should not exceed 1 s.
As well, during this transient response, the output
signal shall not change its phase position in time
faster than 81 ns per 1.326 ms observation period.
For the case where the PRI and SEC reference
inputs are both at 8 kHz, but phase separated by
180 the maximum time interval recorded for input
rearrangement is 320 ns. For a 45 degree separation
of
rearrangement indicated a measured slope of 10ns
per 1.326 ms observation period.
Jitter Performance
The output jitter of a digital trunk PLL is composed of
intrinsic jitter, measured using a jitter free reference
clock, and frequency dependent jitter, measured by
applying known levels of jitter on the references
clock. The jitter spectrum indicates the frequency
content of the output jitter.
Intrinsic Jitter
Intrinsic jitter is the jitter added to an output signal by
the processing device, in this case the enhanced
PLL. Tables 6 and 7 show the average measured
intrinsic jitter of the T1 and E1 outputs.
measurement is an average based upon a 100 ppm
deviation (in steps of 20 ppm) on the input reference
clock. Jitter on the master clock will increase intrinsic
Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing
Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing
Reference Input
the
Reference Input
1.544 MHz
2.048 MHz
8 kHz
1.544 MHz
2.048 MHz
reference
8 kHz
inputs,
FLT0 Unfiltered
Table 7 - Typical Intrinsic Jitter for the E1 Output
an
Table 6 -Typical Intrinsic Jitter for the T1 Output
.011
.011
.011
FLT0 Unfiltered
85
.011
.011
.011
Hz
Output Jitter in UIp-p
Output Jitter in UIp-p
periodic
Each
10Hz - 8kHz
FLT1
.004
.001
.001
jitter of the device, hence attention to minimization of
master clock jitter is required.
Jitter Transfer Function
The jitter transfer function is a measure of the
transfer characteristics of the PLL to frequency
specific jitter on the referenced input of the PLL. It is
directly linked to the loop bandwidth and the
magnitude
characteristics of the PLL. It is measured by applying
jitter of specific magnitude and frequencies to the
input of the PLL, then measuring the magnitude of
the output jitter (both filtered and unfiltered) on the
T1 or E1 output.
Care must be taken when measuring the transfer
characteristics to ensure that critical jitter alias
frequencies are included in the measurement (i.e.,
for digital phase locked loops using an 8 kHz input).
Tables 8 and 9 provide measured results for the jitter
transfer characteristics of the PLL for both a 1.544
MHz and 2.048 MHz reference input clock. The
transfer characteristics for an 8 kHz reference input
will be the same.
Figures 5 and 6 show the jitter attenuation
performance of the T1 and E1 outputs plotted
against AT & T TR62411 and ETSI requirements,
respectively.
20Hz - 100kHz
FLT1
.002
.002
.002
10Hz - 40kHz
of
FLT2
.006
.002
.002
the
phase
700Hz - 100kHz
error
8kHz - 40kHz
FLT2
.
.
.002
.002
.002
MT9042
FLT3
.002
.001
.001
suppression
3-103