MT933 Zarlink Semiconductor, MT933 Datasheet - Page 2

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MT933

Manufacturer Part Number
MT933
Description
MT933 - 3.3V 10/100 Fast Ethernet Transceiver to Mii
Manufacturer
Zarlink Semiconductor
Datasheet
2
MT933
Functional Description
The MT933 has three basic modes of operation:
10BASE-T, 100BASE-TX and LOW POWER modes.
The Control block is designed to manage these
modes by starting and stopping the 10M and 100M
transceivers in a well-controlled manner such that no
spurious signals are output on either the MII or
twisted-pair interfaces. Furthermore, it continuously
monitors the behaviour of the transceivers and takes
corrective action if a fault is detected.
Other modes described herein are repeater mode
and reset mode.
25MHz Reference Clock
The MT933 requires a 25MHz +/-100ppm timing
reference for 802.3 compatible operation. This may
be supplied either from the integrated oscillator or
from an external source. When the integrated oscillator
is used, a suitable crystal must be connected across
the XTAL1 & XTAL2 pins (see “External Components”)
and REFCLK must be tied low. When an external
source is used, it must be input to the REFCLK pin
and XTAL1 must be tied low. XTAL2 must be
unconnected.
SUBGND2 1
RXGND3 10
RXGND2 16
RESETN 14
RXVDD2 15
RXVDD3 9
SPDST 12
DGND1 3
LNKST 5
ACTST 6
COLST 7
DVDD1 8
TX_ER 2
TX_EN 4
FDST 11
PA4 13
Figure
2Pin connections
10Base-T Operation
10Mb/s Data Transfer on the MII
10Mb/s data is transferred across the MII with clock
speeds of 2.5MHz. The MAC outputs data to the
MT933 via the MII interface, on the TXD[3:0] bus.
This data is synchronised to the rising edge of
TX_CLK. To indicate that there is valid data for
transmission on the MII, the MAC sets the TX_EN
signal active. This forces the MT933 device to take in
the data on the TXD[3:0] bus. This is serialised and
directly encoded as Manchester data, before being
output on the TXOP/TXON differential output for
transmission through 1:Ö2 magnetics and onto the
twisted-pair.
The transmit current is governed by the current through
the TXREF10 pin, which must be grounded through
a resistor as described in “External Components”.
RX10 Clock Recovery
The MT933 employs a digital delay line controlled by
the 100MHz Synthesizer DLL to derive a sampling
clock from the incoming signal. The recovered clock
runs at twice the data rate (nominally 20MHz). When
a signal is received from the Signal Detect block, it is
used to strobe Link Pulses and Manchester encoded
serial data.
33 TXGND3
48 MINT
47 DVDD3
35 TXREF10
34 TXVDD3
46 MDC
45 MDIO
44 DGND3
43 RefCLK
42 OSCVDD
41 XTAL1
40 XTAL2
39 OSCGND
38 TXGND4
37 TXVDD4
36 TXREF100
TP64

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