MPC8280 Motorola, MPC8280 Datasheet - Page 3

• Manufacturer Part Number: MPC8280
• Description: PowerQUICC II Family Hardware Specifications
• Manufacturer: Motorola

Figure 1 shows the block diagram. Shaded portions are device-specific; refer to the notes below.
1.1
The major features of the MPC8280 are as follows:
MOTOROLA
MCC1
Notes:
1
2
3
MPC8280, MPC8275VR, MPC8275ZQ only (not on MPC8270, MPC8270VR, nor MPC8270ZQ)
MPC8280 only (not on MPC8270, the VR package, nor the ZQ package)
MPC8280 has 2 serial interface (SI) blocks and 8 TDM ports. MPC8270 and the VR and ZQ packages have
Parallel I/O
Generators
Baud Rate
•
Timers
only 1 SI block and 4 TDM ports (TDM2[A–D]).
1
G2_LE Core
MCC2
Dual-issue integer (G2_LE) core
— A core version of the EC603e microprocessor
— System core microprocessor supporting frequencies of 166–450 MHz
— Separate 16-Kbyte data and instruction caches:
— PowerPC™ architecture-compliant memory management unit (MMU)
— Common on-chip processor (COP) test interface
Features
– Four-way set associative
– Physically addressed
– LRU replacement algorithm
Communication Processor Module (CPM)
FCC1
TC Layer Hardware
Controller
8 TDM Ports
Interrupt
32-bit RISC Microcontroller
FCC2
MPC8280 PowerQUICC II™ Family Hardware Specifications
and Program ROM
FCC3
2
Instruction
1
32 KB
16 Kbytes
16 Kbytes
RAM
D-Cache
I-Cache
D-MMU
I-MMU
SCC1
Figure 1. MPC8280 Block Diagram
Microcode
32 KB
SCC2
Data
RAM
IMA
3 MII or RMII
1
SCC3
Ports
Time Slot Assigner
Serial Interface
4 Virtual
IDMAs
DMAs
Serial
SCC4/
USB
2 UTOPIA
Ports
SMC1
2
3
System Interface Unit
SMC2
Memory Controller
Bus Interface Unit
System Functions
Clock Counter
60x-to-Local
60x-to-PCI
Non-Multiplexed
Bridge
Bridge
(SIU)
SPI
I/O
I
2
C
32 bits, up to 100 MHz
32 bits, up to 66 MHz
60x Bus
Local Bus
PCI Bus
or
Overview
3