MT8930CE Zarlink Semiconductor, MT8930CE Datasheet - Page 13

• Manufacturer Part Number: MT8930CE
• Description: Description = 4 Wire Full-duplex 2B+D (192Kb/s) Data Format Isdn S And T Subscriber Network Interface Circuit With Controllerless Mode ;; Package Type = Pdip ;; No. Of Pins = 28
• Manufacturer: Zarlink Semiconductor

Data Sheet
Up to eight SNICs in NT mode with physically
independent S-Busses can be connected in parallel
to realize a star configuration, as shown in Figure 14.
All devices connected into the star will carry the
same input, thus information is sent to all TEs
simultaneously. The 2B+D data received from every
TE is transmitted to all NTs through the STAR pin.
Consequently, all the DSTo streams will carry
identical 2B+D data reflecting what is being
transmitted by the various TEs.
The flow of data in the direction of S-Bus to ST-BUS
is transparent to the SNIC, regardless of the state
machine status. On the other hand, the flow of data
in the direction of ST-BUS to S-Bus becomes
transparent only after the state machine is in the
active state (IS0, IS1=1,1), in case of an NT, or in the
synchronization state (IS0, IS1=1), in case of a TE.
Microprocessor/Control Interface
The parallel port on the SNIC operates as either a
general purpose microprocessor interface or as a
hardwired control port.
In microprocessor control mode (Cmode = 1), the
parallel port is compatible with either Motorola or
ST-BUS Clock
ST-BUS Stream
Frame Pulse
Frame Pulse
ST-BUS
Stream
System
System
Input
to TE
to TE
F0b
MT8930C
to TE
NT
F0od
Channel 0 - 3
Active on
Figure 13 - Daisy Chaining the SNIC
Figure 14 - NT in Star Configuration
MT8930C
MT8930C
NT
NT
STAR
STAR
DSTi
DSTi
F0b
F0b
F0b
MT8930C
to TE
NT
V
DD
F0od
Channels 4 - 7
Active on
Intel multiplexed bus signals and timing.
MOTEL
Compatible bus) uses the level of the DS/RD pin
at the rising edge
appropriate
rising edge of AS/ALE (refer Fig. 26) then Motorola
bus timing is selected. Conversely, if DS/RD is
high at the rising edge of AS/ALE (refer Figs. 24 &
25), then Intel bus timing is selected. This has the
effect
transparently to the user.
In this mode, the user has the option of writing to the
C-channel Control or Diagnostic Register through
the parallel port interface or through the C-channel
on DSTi.
provides this option.
The parallel port on the SNIC allows complete
control of the HDLC transceiver and access to all
data, control and status registers. The internal
registers (defined in Table 2) can be accessed
through the microprocessor port only when the
Cmode pin is held high.
allows the microprocessor to monitor incoming data
on the S or ST-BUS without interrupting the normal
data flow.
STAR
F0b
DSTi
DSTo
STAR
F0b
DSTi
F0b
MT8930C
MT8930C
MT8930C
of
to TE
NT
NT
NT
Bit 0 of the Master Control Register
F0od
circuit
redefining
Channels 8 - 11
bus timing.
Active on
of
(MOtorola
to TE
to TE
the
F0b
AS/ALE
MT8930C
Reading these registers
to TE
If DS/RD is low at the
NT
microprocessor
F0od
Channels 12 - 15
ST-BUS Stream
Active on
to
and
Output
select
InTEL
The
port
the
13