MT8930CE Zarlink Semiconductor, MT8930CE Datasheet - Page 15

• Manufacturer Part Number: MT8930CE
• Description: Description = 4 Wire Full-duplex 2B+D (192Kb/s) Data Format Isdn S And T Subscriber Network Interface Circuit With Controllerless Mode ;; Package Type = Pdip ;; No. Of Pins = 28
• Manufacturer: Zarlink Semiconductor

Data Sheet
Diagnostic Register cleared. Once full activation is
achieved the Diagnostic Register can be written to in
order to enable the various test functions.
HDLC Transceiver
The HDLC Transceiver handles the bit oriented
protocol structure and formats the D-channel as per
level 2 of the X.25 packet switching protocol defined
by CCITT. It transmits and receives the packetized
data (information or control) serially in a format
shown
transparency by zero insertion and deletion.
generates and detects the flags, various link channel
states and the abort sequence. Further, it provides a
cyclic redundancy check on the data packets using
the CCITT defined polynomial. In addition, it can
recognize a single byte, dual byte or an all call
address in the received frame.
provision to disable the protocol functions and
provide transparent access to either serial port
through the microprocessor port.
provided by the HDLC include, independent port
selection for transmit and received data (e.g.
transmit on S-Bus and receive from ST-BUS),
selectable 16 or 64 kbit/s D-channel as well as an
HDLC loopback from the transmit to the receive port.
These features are enabled through the HDLC
control registers (see Tables 6 and 7).
HDLC Frame Format
All frames start with an opening flag and end with a
closing flag as shown in Figure 15. Between these
two flags, a frame contains the data and the frame
check sequence (FCS).
i) Flag
The flag is a unique pattern of 8 bits (01111110)
defining the frame boundary. The transmit section
generates the flags and appends them automatically
to the frame to be transmitted. The receive section
searches the incoming packets for flags on a
bit-by-bit
synchronization. The flags are used only to identify
and synchronize the received frame and are not
transferred to the FIFO.
FLAG
Byte
One
in
Figure 15 - Frame Format
basis
Figure
DATA FIELD
n Bytes
(n ≥ 2)
15,
and
while
establishes
Bytes
There is also a
FCS
Two
providing
Other features
FLAG
Byte
One
frame
data
It
ii) Data
The data field refers to the Address, Control and
Information
recommendations. A valid frame should have a data
field of at least 16 bits. The first and second byte in
the data field is the address of the frame.
iii) Frame Check Sequence (FCS)
The 16 bits following the data field are the frame
check sequence bits. The generator polynomial is:
The transmitter calculates the FCS on all bits of the
data field and transmits the complement of the FCS
with most significant bit first. The receiver performs
a similar computation on all bits of the received data
but also includes the FCS field.
polynomial will assure that if the integrity of of the
transmitted data was maintained, the remainder will
have a consistent pattern and this can be used to
identify, with high probability, any bit errors occurred
during transmission. The error status of the received
packet is indicated by B7 and B6 bits in the HDLC
Status Register.
iv) Zero Insertion and Deletion
The transmitter, while sending either data from the
FIFO or the 16 bits FCS, checks the transmission on
a bit-by-bit basis and inserts a ZERO after every
sequence of five contiguous ONEs (including the last
five bits of FCS) to ensure that the flag sequence is
not imitated.
incoming frame content and discards any ZERO
directly following the five contiguous ONEs.
v) Abort
The transmitter aborts a frame by sending a zero
followed by seven consecutive ONEs. The FA bit in
the HDLC Control Register 2 along with a write to the
HDLC Transmit FIFO enables the transmission of an
abort sequence instead of the byte written to the
register (to have a valid abort there must be at least
two bytes in the packet).
frame abort is defined as seven or more contiguous
ONEs occurring after the start flag and before the
end flag of a packet. An interrupt can be generated
on reception of the abort sequence using FA bit in
the HDLC Interrupt Mask/Vector Registers (refer to
Tables 9 and 10).
fields
Similarly the receiver examines the
G(x)=x
defined
16
+x
12
On the receive side, a
+x
5
+1
in
The generating
the
CCITT
15