MPC89L52A Megawin Technology, MPC89L52A Datasheet - Page 14

• Manufacturer Part Number: MPC89L52A
• Description: 8-bit micro-controller
• Manufacturer: Megawin Technology

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EXF2: Timer2 external flag. It will be set when either a capture or reload is caused by a negative transition
TF0: =Timer0 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when the
TCLK: When set causes the serial port to use Timer2 overflow pulse for it’s transmit clock in mode 1 and
EXEN2: Timer-2 external enable flag. When set, allows a capture or reload to occur. As a result of a
T2OE: Timer 2 Output Enable bit. It enables Timer2 overflow rate to toggle P1.0.
DCEN: Down Count Enable bit. When set, this allows Timer2 to be configured as a down counter.
SFR: TCON
TF1: =Timer1 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when the
TR1: =Timer1 run control bit. Set/Cleared by software.
TR0: =Timer1 run control bit. Set/Cleared by software.
IE1: =Interrupt 1 Edge flag. Set by hardware when external interrupt edge detected. Cleared when interrupt
IT1: =Interrupt 1 type control bit. Set/Cleared by software to specified falling edge/low level triggered
IE0: =Interrupt 0 Edge flag. Set by hardware when external interrupt edge detected. Cleared when interrupt
IT0: =Interrupt 0 type control bit. Set/Cleared by software to specified falling edge/low level triggered
SFR: T2MOD
SFR: T2CON
TF2: Timer2 overflow flag. It will be set by a Timer2 overflow and must be cleared by software.
RCLK: When set causes the serial port to use Timer2 overflow pulse for it’s receive clock in mode and
TR2: Start/Stop control for Timer2.
14
Bit-7
Bit-7
Bit-7
TF1
TF2
TF2 will not be set when either TCLK or RCLK =1.
interrupt.
interrupt.
processed.
processed.
on pin T2EX and EXEN2=1. When Timer2 interrupt is enabled, EXF2=1 will cause the CPU to vector
to the timer2 interrupt routine. EXF2 must be cleared by software. EXF2 does not cause an interrupt
in Auto-Reload Up-Down mode (ARUD).
processor vectors to the interrupt routine, or clearing the bit in software.
processor vectors to the interrupt routine, or clearing the bit in software.
mode 3. RCLK=0 causes Timer1 overflow pulse to be used.
mode 3. RCLK=0 causes Timer1 overflow pulse to be used.
negative transition on T2EX if Timer2 is not being used to clock the serial port.
EXEN2=0 causes Timer2 to ignore events at T2EX.
EXF2
Bit-6
Bit-6
Bit-6
TR1
RCLK
Bit-5
Bit-5
Bit-5
TF0
TCLK
Bit-4
Bit-4
Bit-4
TR0
MPC89x52A Data Sheet
EXEN2
Bit-3
Bit-3
Bit-3
IE1
Bit-2
Bit-2
Bit-2
TR2
IT1
T2OE
C//T2
Bit-1
Bit-1
Bit-1
IE0
CP/RL2
DCEN
Bit-0
Bit-0
Bit-0
IT0
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