mg87fe Megawin Technology, mg87fe Datasheet
mg87fe
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mg87fe Summary of contents
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... In-Application-Programming allow the users to download new code or data while the microcontroller sits in the application. This device executes one machine cycle in 6 clock or 12 clock cycles. MG87FE/L52 has four 8-bit I/O ports, one 4-bit I/O ports, three 16-bit timer/counters, an eight-source, four-priority-level interrupt structure, an enhanced UART, on-chip crystal oscillator ...
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... Megawin Technology Co., Ltd. - PLCC-44 & PQFP-44(MG87FE/L52AP//AF, MG87FE/L52AF//GF) will have 36 I/O ports On-Chip flash program/data memory: - The data endurance of the embedded flash gets over 20,000 times. - Greater than 100 years data retention under room temperature. (at 25℃) Operating Voltage: - 4.5V~5.5V for MG87FE52 - 2.4V~3.6V for MG87FL52, minimum 2.7V requirement in flash write operation - Built-in Low-Voltage-Reset circuit Operating Temperature range from -40° ...
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... Megawin Technology Co., Ltd. 3.0 Package & Pin assignment 3.1 Order Information Preliminary ver 1.3 Date: 2009-JAN-20 MG87FE/L52 3 ...
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... As inputs, port 2 pins that are 23 externally pulled low will source current 24 because of the internal pull-ups. 25 Except being as GPIO, Port2 emits the high-order address accessing to external program and data memory. Preliminary ver 1.3 Date: 2009-JAN-20 MG87FE/L52 used as one of bytes during 4 ...
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... An internal pull-up resistor has been embedded in this pin Input to the amplifier Output from the inverting amplifier. Preliminary ver 1.3 Date: 2009-JAN-20 MG87FE/L52 timer0 and timer1 inverting oscillator 5 ...
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... Megawin Technology Co., Ltd. VDD 40 44 VSS Power Supply 16 G Ground Preliminary ver 1.3 Date: 2009-JAN-20 MG87FE/L52 6 ...
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... Megawin Technology Co., Ltd. 5.0 Block Diagram of MG87FE/L52 Preliminary ver 1.3 Date: 2009-JAN-20 MG87FE/L52 7 ...
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... Megawin Technology Co., Ltd. 6.0 Special Function Registers (SFR) Preliminary ver 1.3 Date: 2009-JAN-20 MG87FE/L52 8 ...
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... Megawin Technology Co., Ltd. Preliminary MG87FE/L52 ver 1.3 Date: 2009-JAN-20 9 ...
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... Megawin Technology Co., Ltd. 7.0 Memory: Data RAM Addressing & Program Flash ROM 7.1 Organization Address Space for MG87FE/L52 RAM Address Space for MG87FE/L52 Embedded Flash Memory Preliminary ver 1.3 Date: 2009-JAN-20 MG87FE/L52 10 ...
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... Note-1: When OSCDN option was enabled, the power consumption could be lower. 7.3 Data RAM Addressing MG87FE/L52 has internal data RAM that is mapped to three separated segments. The lower 128 bytes of RAM, upper 128 bytes of RAM and 128 bytes Special Function Register(SFR). Lower 128 bytes of RAM: (addresses 0x00 to 0x7F) are accessed by either direct or indirect addressing ...
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... Bit5 Bit4 Bit3 - - GF2 Bit5 Bit4 Bit3 - - - SCKS2 SCKS0 CLKin(System Clock Preliminary ver 1.3 MG87FE/L52 Bit2 Bit1 Bit0 - - AO Bit2 Bit1 Bit0 - - DPS Bit2 Bit1 Bit0 SCKS1 SCKS0 OSCin OSCin/2 OSCin/4 OSCin/8 OSCin/16 OSCin/32 OSCin/64 OSCin/128 12 Date: 2009-JAN-20 ...
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... Regarding application not needing high frequency clock recommended to do so. =0, MG87FE/L52 will run in 12T mode; EN6TR =1, MG87FE/L52 will run in 6T mode. It gets double performance than 12T. The default value of this bit is load from Option Setting “EN6T”. Set the crystal frequency value to define the time base of ISP/IAP programming. XCKS5~0 Fill in the proper value according to XTAL1 as listed below ...
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... Megawin Technology Co., Ltd. 12T XTAL1 Oscillating X 2 Circuit XTAL2 CKCON2.EN6TR Figure 7-3-2 Preliminary MG87FE/L52 ISP/IAP Logic XCKS[5:0] 0 OSCin SCKS[2: ver 1.3 Date: 2009-JAN-20 CLKin (System Clock) 14 ...
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... Timer0, Timer1 & Timer2 8.1 Timers/Counters MG87FE/L52 has three 16-bit timers, and they are named T0, T1 and T2. Each of them can also be used as a general event counter, which counts the transition from While T0/T1/T2 is used as “timer” function, the time unit that used to measure the timer is machine cycle ...
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... Interrupt-0 edge flag. Set by hardware when external interrupt edge detected. And IE0 cleared when interrupt processed. Interrupt 0 type control bit. Set/Cleared by software to specified falling edge/low level IT0 triggered interrupt. Bit5 Bit4 Bit3 TF0 TR0 IE1 Preliminary ver 1.3 MG87FE/L52 Bit2 Bit1 Bit0 IT1 IE0 IT0 16 Date: 2009-JAN-20 ...
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... TCLK or RCLK is 1, this bit is ignored and the timer is forced to auto-reload on Timer2 overflow. Bit5 Bit4 Bit3 - - - It enables Timer2 overflow rate to toggle P1.0 Bit5 Bit4 Bit3 RCLK TCLK EXEN2 Preliminary ver 1.3 MG87FE/L52 Bit2 Bit1 Bit0 - T2OE DCEN Bit2 Bit1 Bit0 TR2 C//T2 CP/RL2 17 Date: 2009-JAN-20 ...
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... Mode 2 configures the timer register as an 8-bits counter (TLx) with automatic reload. Overflow from TLx does not only set TFx, but also reloads TLx with the content of THx, which is determined by user’s program. The reload leaves THx unchanged. Mode 2 operation is the same for Timer0 and Timer1. Preliminary ver 1.3 Date: 2009-JAN-20 MG87FE/L52 18 ...
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... Mode 3 enables TL0 and TH0 as two separate 8-bits counters. TL0 uses the Timer0 control bits such like C/T, GATE, TR0, INT0 and TF0. TH0 is locked into a timer function (can not be external event counter) and take over the use of TR1, TF1 from Timer 1. TH0 now controls the Timer 1 interrupt. Preliminary ver 1.3 Date: 2009-JAN-20 MG87FE/L52 19 ...
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... Timer2 is also can be configured as a periodical signal generator. The MG87FE/L52 is able to generate a programmable clock output from P1.0. When T2OE bits is set and C//T2 bits is cleared, Timer2 overflow pulse will generate a 50% duty clock and output to P1.0. The frequency of clock-out is calculated according to the following formula. ...
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... An overflow on Timer2 will set TF2 and toggle EXF2. EXF2 can not generate interrupt request in this mode. If the counting direction is DOWN, the overflow loads 0xFFFF onto Timer2 and loads RCAP2H, RCAP2L contents onto Timer2 if counting direction is UP. Preliminary ver 1.3 Date: 2009-JAN-20 MG87FE/L52 21 ...
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... An overflow on Timer2 will load RCAP2H, RCAP2L contents onto Timer2 but TF2 will not be set. A 1-to-0 transition on T2EX pin can set EXF2 to request interrupt service if EXEN2=1. The baud rate in UART Mode-1 and Mode-3 are determined by Timer2’s overflow rate given below: Preliminary ver 1.3 Date: 2009-JAN-20 MG87FE/L52 22 ...
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... Megawin Technology Co., Ltd. 8.4 UART (Universal Asynchronous Receiver & Transmitter interface) The serial port of MG87FE/L52 support full-duplex transmission. It can transmit and receive simultaneously. The serial port receive and transmit share the same SFR – SBUF, but actually there is two SBUFs in the chip, one is for transmitter and the other is for receiver. The serial port could be operated in 4 different modes ...
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... In mode1, the RI flag will be set if SM2 is enabled and a valid stop bit is received which the stop bit follows the 8 address bits and the information is either a Given or Broadcast address. In mode 0, SM2 is ignored. th received bit indicate that Preliminary ver 1.3 Date: 2009-JAN-20 MG87FE/L52 24 ...
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... In mode 2 and 3, the received 9th data bit will go into this bit. TI Transmit interrupt flag. RI Receive interrupt flag. Bit5 Bit4 Bit3 SM2 REN TB8 Baud Rate CLKin/12 Variable CLKin/64 or CLKin/32 Variable * Please refer to page-14 figure 7-3-2 for “CLKin” signal. Preliminary ver 1.3 MG87FE/L52 Bit2 Bit1 Bit0 RB8 Date: 2009-JAN-20 ...
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... SADEN. Zero in this result is considered as “don’t care”. Upon reset, SADDR and SADEN are loaded with all 0s. This produces a Given-Address of all “don’t care” and a Broadcast Address of all “don’t care”. This disables the automatic address detection feature. Preliminary ver 1.3 Date: 2009-JAN-20 MG87FE/L52 26 ...
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... Power-Down mode was woken-up from I/O, the program will jump to related interrupt vector service routine. To use I/O wake-up, interrupt-related registers have to be programmed accurately before power-down is entered. User should be noted to add at least one “NOP” instruction subsequent to the power-down instruction if I/O waken-up is used. Preliminary ver 1.3 Date: 2009-JAN-20 MG87FE/L52 27 ...
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... RESET and RESET pin can not set POF. It only can be cleared by firmware. ALE PSEN Port0 Port1 1 1 Data Data 1 1 Float Data 0 0 Data Data 0 0 Float Data Preliminary ver 1.3 Date: 2009-JAN-20 MG87FE/L52 Port2 Port3 Data Data Address Data Data Data Data Data 28 ...
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... If set, Set priority for external interrupt 1 highest Bit5 Bit4 Bit3 ET2 ES ET1 Bit5 Bit4 Bit3 PT2 PS PT1 Bit5 Bit4 Bit3 PT2H PSH PT1H Preliminary ver 1.3 MG87FE/L52 Bit2 Bit1 Bit0 EX1 ET0 EX0 Bit2 Bit1 Bit0 PX1 PT0 PX0 Bit2 Bit1 Bit0 PX1H PT0H PX0H 29 Date: 2009-JAN-20 ...
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... Interrupt 2 types control bits. Set/Cleared by software to specify falling edge/low IT2 level triggered interrupt. There are eight interrupt sources available in MG87FE/L52. Each interrupt source can be individually enabled or disabled by setting or clearing a bit in the SFR named IE. This register also contains a global disable bit(EA), which can be cleared to disable all interrupts at once. ...
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... All of the bits that generate interrupts can be set or cleared by software, with the same result as though it had been set or cleared by hardware. In other words, interrupts can be generated or pending interrupts can be canceled in software. Vector address Priority within level 03H 0BH 13H 1BH 23H 2BH 33H 3BH Preliminary ver 1.3 Date: 2009-JAN-20 MG87FE/L52 1 (highest ...
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... PS2 ~ PS1: select the pre-scaler output. PS2 PS1 PS0 Bit5 Bit4 Bit3 ENW CLRW WIDL Pre-scaler value 128 256 Preliminary ver 1.3 MG87FE/L52 Bit2 Bit1 Bit0 PS2 PS1 PS0 32 Date: 2009-JAN-20 ...
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... In-System-Programming & In-Application Programmable 12.0 In-System-Programming (ISP) In MG87FE/L52, 8K bytes flash ROM is divided into three sections. The first partition named AP-memory is the space for storing user’s application program code. The next one named LD-memory is the space which ISP program is loaded. The third one named OR-memory space has option registers here ...
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... Additional attention point, the IAP low boundary address must not be higher than ISP start address. Bit5 Bit4 Bit3 Reserved Mode Standby AP-memory read AP-memory program AP-memory page erase IAPLB write IAPLB read Bit5 Bit4 Bit3 Data Preliminary ver 1.3 MG87FE/L52 Bit2 Bit1 Bit0 Mode Selection Bit2 Bit1 Bit0 34 Date: 2009-JAN-20 ...
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... The flash memory between IAPLB and ISP start address could be defined as data flash memory and can be accessed by the ISP operation in field application. The size of IAP flash memory is variable defined by IAPLB. When the MG87FE/L52 was boots from LD-memory, AP-memory and data flash memory are opened for ISP operation. Bit5 ...
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... Megawin Technology Co., Ltd. 13 System Oscillator 13.1 External crystal mode MG87FE/L52 built-in two kinds of oscillator for MCU system clock operating. The first one is crystal oscillator & it can support 6MHz ~ 48MHz/12T or 6MHz ~ 24MHz/6T with external crystal component. Please refer to the figure 13-1. VDD=5/3V XTL 1 6MHz 2 11 ...
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... Megawin Technology Co., Ltd. 14.0 Absolute Maximum Rating MG87FE52: (5.0V application) Parameter Ambient temperature under bias Storage temperature Voltage on any Port I/O Pin or RST with respect to Ground Voltage on VDD with respect to Ground Maximum total current through VDD and Ground Maximum output current sunk by any Port pin *Note: stresses above those listed under “ ...
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... Megawin Technology Co., Ltd Characteristics 15.1 MG87FE52 DC Characteristics VDD = 5.0V, VSS = 0V ℃ and 12 clocks per machine cycle, unless otherwise specified Symbol Parameter V Input High voltage (Ports IH1 V Input High voltage (RESET) IH2 V Input Low voltage (Ports IL1 V Input Low voltage (RESET) ...
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... Megawin Technology Co., Ltd. 16 Package Dimension 16.1 40-Pin PDIP Package (MG87FE/L52AE) Preliminary ver 1.3 Date: 2009-JAN-20 MG87FE/L52 39 ...
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... Megawin Technology Co., Ltd. 16.2 44-Pin PLCC Package (MG87FE/L52AP) Preliminary ver 1.3 Date: 2009-JAN-20 MG87FE/L52 40 ...
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... Megawin Technology Co., Ltd. 16.3 44-Pin PQFP Package (MG87FE/L52AF) Preliminary ver 1.3 Date: 2009-JAN-20 MG87FE/L52 41 ...
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... Right to Make Changes — Megawin reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in mass production, relevant changes will be communicated via an Engineering Change Notification (ECN). Preliminary ver 1.3 Date: 2009-JAN-20 MG87FE/L52 42 ...
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... Modified page-38 I Ver1.2 Added Internal oscillator description. Ver 1.3 Added external crystal Resistor & capacitor list 2008/12/25 Ver 1.4 Modified package form & order information Description 2008/10/17 & I current. 2008/11/24 IDLE OP 2008/12/20 2009/04/18 Preliminary ver 1.3 MG87FE/L52 Date Page & Date: 2009-JAN-20 ...
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... Megawin Technology Co., Ltd. Preliminary MG87FE/L52 ver 1.3 Date: 2009-JAN-20 44 ...