mg87fe Megawin Technology, mg87fe Datasheet - Page 33

• Manufacturer Part Number: mg87fe
• Description: 8 Bits Microcontroller
• Manufacturer: Megawin Technology

12 In-System-Programming & In-Application Programmable
12.0 In-System-Programming (ISP)
In MG87FE/L52, 8K bytes flash ROM is divided into three sections. The first partition named
AP-memory is the space for storing user’s application program code. The next one named
LD-memory is the space which ISP program is loaded. The third one named OR-memory space
has option registers here.
Three-level code protection from read-out on the programmer is implemented in this chip. The
first-level is LOCK bit. If LOCK bit was enabled (programming to 0), the data readout on the
programmer will always be 0xFFh. SCRAMBLE bit is the second level protection. Enabling
SCAMBLE bit encrypts the data readout on the programmer. The third level protection is
MOVCL. Enabling MOVCL inhibits MOVC operation in the condition that the execution is from
external fetch but the target code byte is in internal flash memory.
IFD (ISP Flash Data register)
IFD is the data port register for ISP/IAP operation. The data in IFD will be written into the desired
address in operating ISP/IAP write and it is the data window of readout in operating ISP/IAP
read.
If IMFT is indexed on IAPLB access, read/write IFD through SCMD flow will access the register
content of IAPLB.
IFADRH (ISP Address for High-byte addressing)
IFADRH
IFADRH is the high-byte address port for all ISP/IAP modes.
IFADRL (ISP Address for Low-byte addressing)
IFADRL is the low byte address port for all ISP/IAP modes. In page erase operation, it is ignored.
IFADRL
Name
Name
Name
IFD
Bit7
Bit7
Bit7
Megawin Technology Co., Ltd.
Bit6
Bit6
Bit6
Bit5
Bit5
Bit5
Preliminary
Bit4
Bit4
Bit4
Address
Address
Data
ver 1.3
Bit3
Bit3
Bit3
Bit2
Bit2
Bit2
Date: 2009-JAN-20
MG87FE/L52
Bit1
Bit1
Bit1
Bit0
Bit0
Bit0
33