mg87fe Megawin Technology, mg87fe Datasheet - Page 27

• Manufacturer Part Number: mg87fe
• Description: 8 Bits Microcontroller
• Manufacturer: Megawin Technology

MG87FE/L52
Megawin Technology Co., Ltd.
9.0 RESET & Power Saving Mode
9.1 RESET
The RESET pin is used to reset this device. It is connected into the device to a Schmitt Trigger
buffer to get excellent noise immunity. Any positive pulse from RESET pin must be kept at least
two-machine cycle, or the device cannot be reset.
9.2 Power saving mode
There are two kinds of power saving modes which are selectable to drive the MG87FL/E52 to
enter power-saving mode.
9.2.1 Idle Mode
The user can set the bits PCON.0 to drive this chip entering IDLE mode.
In the IDLE mode, the internal clock is gated off to the CPU, but not to the interrupt, timer and
serial port functions.
There are two ways to release from the idle mode. Activation of any enabled interrupt sources
will cause PCON.0 to be cleared by hardware to terminating the idle mode. The interrupt will be
serviced and following RETI, the next instruction to be executed will be performed right after the
instruction that causes the device entering the idle mode. Another way to wake-up from idle is
to pull RESET pin high to generate internal hardware reset.
9.2.2 Power-Down Mode
The user can set the bits PCON.1 to drive this chip entering Power-Down mode.
In the Power-Down mode, the on-chip oscillator is stopped. The contents of on-chip RAM and
SFRs are maintained.
The Power-Down mode can be woken-up by either hardware reset or /INT0, /INT1, /INT2 and
/INT3 external interrupts. When it is woken-up by RESET pin, the program will execute from the
address 0x0000, and be carefully to keep RESET pin active for at least 10ms in order to get a
stable clock while waking up this chip from Power-Down mode. If it was woken-up from I/O, the
program will jump to related interrupt vector service routine. To use I/O wake-up,
interrupt-related registers have to be programmed accurately before power-down is entered.
User should be noted to add at least one “NOP” instruction subsequent to the
power-down instruction if I/O waken-up is used.
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Preliminary
ver 1.3
Date: 2009-JAN-20