MT8931C Zarlink Semiconductor, MT8931C Datasheet - Page 14

• Manufacturer Part Number: MT8931C
• Description: 4 Wire Full-duplex 2B+D (192 Kbps) Data Format Isdn S And T Subscriber Network Interface Circuit
• Manufacturer: Zarlink Semiconductor

14
MT8931C
ii) Data
The data field refers to the Address, Control and
Information
recommendations.
data field of at least 16 bits. The first and second
byte in the data field is the address of the frame.
iii) Frame Check Sequence (FCS)
The 16 bits following the data field are the frame
check sequence bits. The generator polynomial is:
The transmitter calculates the FCS on all bits of the
data field and transmits the complement of the FCS
with most significant bit first. The receiver performs
a similar computation on all bits of the received data
but also includes the FCS field.
polynomial will assure that if the integrity of of the
transmitted data was maintained, the remainder will
have a consistent pattern and this can be used to
identify, with high probability, any bit errors occurred
during transmission.
received packet is indicated by B7 and B6 bits in the
HDLC Status Register.
iv) Zero Insertion and Deletion
The transmitter, while sending either data from the
FIFO or the 16 bits FCS, checks the transmission
on a bit-by-bit basis and inserts a ZERO after every
sequence of five contiguous ONEs (including the
last five bits of FCS) to ensure that the flag
sequence is not imitated.
examines the incoming frame content and discards
any ZERO directly following the five contiguous
ONEs.
v) Abort
The transmitter aborts a frame by sending a zero
followed by seven consecutive ONEs. The FA bit in
the HDLC Control Register 2 along with a write to
the HDLC Transmit FIFO enables the transmission
of an abort sequence instead of the byte written to
the register (to have a valid abort there must be at
least two bytes in the packet). On the receive side,
a frame abort is defined as seven or more
contiguous ONEs occurring after the start flag and
before the end flag of a packet. An interrupt can be
generated on reception of the abort sequence using
FA bit in the HDLC Interrupt Mask/Vector Registers
(refer to Tables 9 and 10).
fields
G(x)=x
A valid frame should have a
16
defined
The error status of the
+x
12
+x
Similarly the receiver
5
+1
in
The generating
the
CCITT
Interframe Time Fill
When the HDLC Tranceiver is not sending packets,
the transmitter can be in one of two states
mentioned below depending on the status of the
IFTF bit in the HDLC Control Register 1.
i) Idle State
The Idle state is defined as 15 or more contiguous
ONEs. When the HDLC Protocoller is observing
this condition on the receiving channel, the Idle bit
in the HDLC Status Register is set HIGH. On the
transmit side, the Protocoller ends the transmission
of all ones (idle state) when data is loaded into the
transmit FIFO.
CCITT I.430 Specification requires every TE that
does not have layer 2 frames to transmit, to send
binary ONEs on the D-channel.
other TEs on the line will have the opportunity to
access the D-channel using the priority mechanism
circuitry.
ii) Flag Fill State
The HDLC Protocoller transmits continuous flags
(7E
state when data is loaded into the transmit FIFO.
The reception of the interframe time fill will have the
effect of setting the idle bit in the HDLC Status
Register is set to ’0’.
HDLC Transmitter
On power up, the HDLC transmitter is disabled and
in the idle state.
setting the TxEN bit in the HDLC Control Register 1.
To start a packet, the data is written into the 19 byte
Transmit FIFO starting with the address field. All
the data must be written to the FIFO in a bytewide
manner. When the data is detected in the transmit
FIFO, the HDLC protocoller will proceed in one of
the following ways:
1)
2)
Hex
If the transmitter is in idle state, the present
If the transmitter is in the flag fill state,
byte of ones is completely transmitted before
sending the opening flag. The data in the
transmit FIFO is then transmitted.
transmitting on the D-channel will use the
contention circuitry described previously in D-
channel Priority Mechanism to access this
channel.
) in Interframe Time Fill state and ends this
The transmitter is enabled by
In this manner,
Data Sheet
A TE