MT8931CP Zarlink Semiconductor, MT8931CP Datasheet - Page 15

• Manufacturer Part Number: MT8931CP
• Description: Description = 4 Wire Full-duplex 2B+D (192Kb/s) Data Format Isdn S And T Subscriber Network Interface Circuit ;; Package Type = Pdip ;; No. Of Pins = 28
• Manufacturer: Zarlink Semiconductor

3)
To indicate that the particular byte is the last byte of
the packet, the EOP bit in the HDLC Control Register
2 must be set before the last byte is written into the
transmit FIFO. The EOP bit is cleared automatically
when the data byte is written to the FIFO. After the
transmission of the last byte in the packet, the frame
check sequence (16 bits) is sent followed by a
closing flag. If there is any more data in the transmit
FIFO, it is immediately sent after the closing flag.
That is, the closing flag of a packet is also used as
the opening flag the the next packet.
However,
Recommendations state that after the successful
transmission of a packet, a TE must lower its priority
level within the specified priority class. The user can
meet this requirement by loading the Tx FIFO with no
more than one packet and then waiting for the
DCack bit to go to zero, or for an HDLC interrupt by
the TEOP bit in the HDLC Interrupt Status Register,
before attempting to load a new packet. If there is no
more data to be transmitted, the transmitter assumes
the selected link channel state.
During the transmission of either the data or the
frame check sequence, the Protocol Controller
checks the transmitted information on a bit by bit
basis to insert a ZERO after every sequence of five
consecutive ONEs. This is required to eliminate the
possibility of imitating the opening or closing flag, the
idle code or an abort sequence.
i) Transmit Underrun
A transmit underrun occurs when the last byte
loaded into the transmit FIFO was not ‘flagged’ with
the ‘end of packet’ (EOP) bit and there are no more
bytes in the FIFO. In such a situation, the Protocol
Controller transmits the abort sequence (zero and
seven ones) and moves to the selected link channel
state.
Conversely, in the event that the transmit FIFO is full,
any further writes will overwrite the last byte in the
Transmit FIFO.
ii) Abort Transmission
Data Sheet
If
the flag presently being transmitted is used as
the opening flag for the packet stored in the
transmit FIFO.
data mode, the protocol functions are disabled
and the data in the transmit FIFO is transmitted
without a framing structure.
the HDLC transmitter
CCITT
I.430
and
is
ANSI
in transparent
T1.605
If it is desired to abort the packet currently being
loaded into the transmit FIFO, the next byte written
to the FIFO should be ‘flagged’ to cause this to
happen. The FA bit of the HDLC Control Register 2
must be set HIGH, before writing the next byte into
the FIFO. This bit is cleared automatically once the
byte is written to the Transmit FIFO.
‘flagged’ byte reaches the bottom of the FIFO, a
frame abort sequence is sent instead of the byte and
the transmitter operation returns to normal.
frame abort sequence is ignored if the packet has
less then two bytes.
iii) Transparent Data Transfer
The Trans bit (B4) in the HDLC Control Register 2
can be set to provide transparent data transfer by
disabling the protocol functions. The transmitter no
longer generates the Flag, Abort and Idle sequences
nor does it insert the zeros and calculate the FCS.
It should be noted that none of the protocol related
status or interrupt bits are applicable in transparent
data transfer state.
status and interrupt bits are pertinent and carry the
same meaning as they do while performing the
protocol functions.
HDLC Receiver
After a reset on power up, the receive section is
disabled. Address detection is also disabled when a
reset occurs. If address detection is required, the
Receiver Address Registers are loaded with the
desired address and the ADRec bit in the HDLC
Control Register 1 is set HIGH. The receive section
can then be enabled by RxEN bit in this same
Control Register 1. All HDLC interrupts are masked,
thus the desired interrupt signal must be unmasked
through the HDLC Interrupt Mask Register. All active
interrupts are cleared by reading the HDLC Interrupt
Status Register.
i) Normal Packets
After initialization as explained above, the serial data
starts to be clocked in and the receiver checks for
the idle channel and flags.
detected, the ‘Idle’ bit in the HDLC Status Register is
set HIGH.
synchronizes itself in a bytewide manner to the
incoming
resynchronizing to the flags until an incoming packet
appears.
bit-by-bit basis, inserted zeros are deleted, the FCS
is calculated and the data bytes are written into the
The incoming packet is examined on a
data
Once a flag is detected, the receiver
stream.
However, the FIFO related
The
If an idle channel is
receiver
When the
keeps
The
15